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PDF SCM69C433 Data sheet ( Hoja de datos )
| Número de pieza | SCM69C433 | |
| Descripción | 16K x 64 CAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM69C433/D
www.DataSheet4U.com
16K x 64 CAM
MCM69C433
SCM69C433
The MCM69C433 is a flexible content–addressable memory (CAM) that can
contain 16K entries of 64 bits each. The widths of the match field and the output
field are programmable, and the match time is designed to be 240 ns. As a result,
the MCM69C433 is well suited for datacom applications such as Virtual Path
Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to
OC12 (622 Mbps) data rates and Media Access Control (MAC) address lookup
C.in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C433 is
INuser–defined, with a trade–off between the time between the match request rate
R,and the rate of new entries added to the CAM per second.
TO• 16K Entries
UC• 240 ns Match Time
ND• Mask Register to “Don’t Care” Selected Bits
ICO• Depth Expansion by Cascading Multiple Devices
M• 66 MHz Maximum Clock Rate
SE• Programmable Match and Output Field Widths
LE• Concurrent Matching of Virtual Path Circuits and Virtual Connection
CACircuits in ATM Mode
ES• Separate Ports for Control and Match Operations
RE• 450 ns Insertion Time if 1 of 14 Entry Queue Locations is Empty
Y F• 120 ms Initialization Time After Fast Insertion (at Power–Up Only)
B• Single 3.3 V ±5% Supply
ED• IEEE Standard 1149.1 Test Port (JTAG)
HIV• 100–Pin TQFP Package
ARCRelated Products
— MCM69C232, MCM69C432, MCM69C233 (CAMs)
TQ PACKAGE
TQFP
CASE 983A–01
CONTROL PORT
A2 – A0
DQ15 – DQ0
SEL
WE
IRQ
DTACK
RESET
KMODE
14 x 64
ENTRY QUEUE
STATUS/
CONTROL
LOGIC
INPUT REG
16K x 64
CAM
TABLE
MATCH PORT
MQ31 – MQ0
K
G
LH/SM
LL
MC
MS
VPC
REV 3
6/11/01
©MMOoTtoOrolRa,OIncL.A20F01AST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69C433•SCM69C433
1
1 page  
Freescale Semiconductor, Inc.
CAPACITANCE (Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance
I/O Capacitance
Symbol
Cin
CI/O
Minwww.DatMaaSxheet4U.Ucnoimt
— 5 pF
— 8 pF
JUNCTION TO AMBIENT THERMAL CHARACTERISTICS
Board
1 Layer
Air (LFPM)
0
θJA (°C/W)
43
1 Layer
200
36
4 Layer
0
33
.4 Layer
200
29
TOR, INCAC OPERATING CONDITIONS AND CHARACTERISTICS
UC(VDD = 3.3 V ±5%, TJ < 120°C, Unless Otherwise Noted)
ICONDInput Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
EMInput Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
ALE SCONTROL PORT TIMINGS
SC(Voltages Referenced to VSS = 0 V, Max’s are tKHKH Dependent and Listed Values are for tKHKH = 15 ns)
EEParameter
Symbol
Min
Y FRAddress Valid to SEL Low
D BDTACK Low to Address Invalid
HIVEData Valid to Select Low
ARCDTACK Low to Data Invalid
tAVSL
tDTLAX
tDVSL
tDTLDX
0
0
0
0
Max
—
—
—
—
Unit Notes
ns
ns
ns
ns
Output Valid to DTACK Low
tQVDTL
2
— ns
WE Valid to Select Low
tWVSL
0
— ns
DTACK Low to WE High
tDTLWH
0
— ns
WE High to Output Active
tWHQX
2
— ns
Select Low to DTACK Low
tSLDTL
10
— ns 1
Select High to DTACK High
tSHDTH
10
— ns
DTACK Low to IRQ Low
tDTLIL
10
— ns
IRQ Low to IRQ High
tILIH
20 — ns
DTACK Low to Select High
tDTLSH
0
— ns
DTACK High to Select Low
tDTHSL
0
— ns
Address Valid to Output Valid
tAVQV
—
8 ns
Select High to Output High Impedance
tSHQZ
—
8 ns
RESET Low to RESET High
tRLRH
2 x tKHKH
NOTE:
1. DTACK is delayed when a write is attempted during certain operations. See Functional Description.
—
ns
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69C433•SCM69C433
5
5 Page 
Freescale Semiconductor, Inc.
2,500
2,000
TYPICAL www.DataSheet4U.com
1,500
1,000
WORST CASE
500
0
20 30 40 50 60 70 80 90 100
MATCH DUTY CYCLE AT 66 MHz INPUT CLOCK
INC.Figure 3. Connections per Second vs Match Cycle Time
OR,insertion and deletion is maximized if the longest–lived en-
CTtries are placed near the beginning of the table and the short-
DUest–lived entries are placed near the end of the table. For an
ONATM application, this would correspond to the assignment of
ICsmall VPI values to permanent virtual circuits and large VPI
EMvalues to switched virtual circuits.
SNote that at start–up, when entries are loaded into the
LECAM via the fast–entry mode, the process is dominated by
CAthe time it takes to execute the initialization instruction that
ESfollows. The resulting effective rate of loading the CAM at
REstart–up is approximately 136,500 entries per second.
BY FRESET
EDAsserting RESET removes all entries from the CAM table
HIVand entry queue. The flag register is set to 1C16 (setting the
Cqueue empty, buffered–entry mode, and table initialized bits).
ARThe error register is set to FFFF16, indicating no errors.
match has been found, the MS output is also asserted. If the
match is a virtual path circuit match in ATM mode, the VPC
output will be asserted with the MS output. Output data, if
any, is enabled by the assertion of the G input.
If the match width is greater than 32 bits, the lower bits are
first latched into the MCM69C433 by the LL input. The match
cycle is then initiated as specified in the previous paragraph.
Two alternative timing diagrams are presented to describe
the Match Port timing. In the first, LH/SM must meet setup
and hold specs across two consecutive clock cycles, while
the MQ bus need only be valid for a single cycle. In the se-
cond diagram, LH/SM need only be asserted for a single
clock cycle, while the MQ bus must be held valid with
constant data across two clock cycles.
SIMULTANEOUS PORT OPERATIONS
When the control and match ports are utilized simulta-
Finally, the almost–full register is set to 3FFF16.
neously, certain procedures must be followed. If a CHECK
TIMING OVERVIEW
FOR VALUE command is issued, both the last operation
complete bit (bit 10) and the entry queue empty bit (bit 4) in
CONTROL PORT
the flag register should be set prior to executing the CHECK
FOR VALUE command in order to receive valid results. How-
The control port of the MCM69C433 is asynchronous.
Data transfers, both read and write, are initiated by the
assertion of the SEL signal. Address values should be valid
and WE should be high, when SEL is asserted to begin
ever, matching on the match port can be done directly after
the last operation complete flag is set.
The match port has priority over the control port during
simultaneous operations.
a read cycle. All values (address, WE, and SEL) should be
held until the MCM69C433 asserts DTACK to signal the end
DEPTH EXPANSION
of the read cycle.
Address and data values should be valid and WE should
be low, when SEL is asserted to begin a write cycle. Address,
data, WE, and SEL values should be held until the
MCM69C433 asserts DTACK to signal the end of the write
cycle.
Multiple CAMs can be cascaded to increase the depth of
the match table. The hardware requirements are very
straightforward, as the following pins on each device are sim-
ply wired in parallel: A2 – A0, DQ15 – DQ0, WE, IRQ,
DTACK, MQ31 – MQ0, K, G, LH/SM, MC, MS, and VPC.
Four CAMs can be easily cascaded. Simulations show that
MATCH PORT
eight devices can be cascaded if care is taken to minimize
the length of the PC board traces connecting the CAMs.
The MCM69C433’s match port is synchronous in opera-
vtion. When the match width is 32 bits, a match cycle can be
The buffered–entry mode prevents multiple matching
entries in a single CAM. The check for value instruction
initiated by presenting the match data on MQ31 – MQ0 and
should be used to verify that multiple matching entries will
asserting the LH/SM signal with the appropriate setup time
not result from a potential new entry. If a match is found in
relative to the rising edge of the clock. The assertion of the
CAM 1, for example, the new value should be placed in CAM 1,
MC output signifies the completion of the match cycle. If a
where it will replace the existing entry.
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69C433•SCM69C433
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet SCM69C433.PDF ] | |
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