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PDF M36L0R8060T1 Data sheet ( Hoja de datos )

Número de pieza M36L0R8060T1
Descripción Multi-Chip Package
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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M36L0R8060T1
M36L0R8060B1
256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
FEATURES SUMMARY
MULTI-CHIP PACKAGE
– 1 die of 256 Mbit (16Mb x16, Multiple
Bank, Multi-level, Burst) Flash Memory
– 1 die of 64 Mbit (4Mb x16) Pseudo SRAM
SUPPLY VOLTAGE
– VDDF = VCCP = VDDQF = 1.7 to 1.95V
– VPPF = 9V for fast program (12V tolerant)
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code
M36L0R8060T1: 880Dh
– Bottom Device Code
M36L0R8060B1: 880Eh
PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
FLASH MEMORY
SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 54MHz
– Asynchronous Page Read mode
– Random Access: 85ns
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
– 10µs typical Word program time using
Buffer Enhanced Factory Program
command
MEMORY ORGANIZATION
– Multiple Bank Memory Array: 16 Mbit
Banks
– Parameter Blocks (Top or Bottom
location)
DUAL OPERATIONS
– program/erase in one Bank while read in
others
– No delay between read and write
operations
SECURITY
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
Figure 1. Package
FBGA
TFBGA88 (ZAQ)
8 x 10mm
BLOCK LOCKING
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WPF for Block Lock-Down
– Absolute Write Protection with VPPF = VSS
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
PSRAM
ACCESS TIME: 70ns
ASYNCHRONOUS PAGE READ
– Page Size: 16 words
– Subsequent read within page: 20ns
LOW POWER FEATURES
– Temperature Compensated Refresh
(TCR)
– Partial Array Refresh (PAR)
– Deep Power-Down (DPD) Mode
SYNCHRONOUS BURST READ/WRITE
June 2005
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M36L0R8060T1 pdf
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M36L0R8060T1, M36L0R8060B1
Table 1. Signal Names
A0-A23
Address Inputs
DQ0-DQ15
Common Data Input/Output
L Latch Enable input for Flash memory and PSRAM
K Burst Clock for Flash memory and PSRAM
WAIT
Wait Data in Burst Mode for Flash memory and PSRAM
VDDF
Flash Memory Power Supply
VDDQF
Flash Power Supply for I/O Buffers
VPPF
Flash Optional Supply Voltage for Fast Program & Erase
VSS Ground
VCCP
PSRAM Power Supply
NC Not Connected Internally
DU Do Not Use as Internally Connected
Flash Memory Signals
EF Chip Enable input
GF Output Enable Input
WF Write Enable input
RPF Reset input
WPF
Write Protect input
PSRAM Signals
EP Chip Enable Input
GP Output Enable Input
WP Write Enable Input
CRP
Configuration Register Enable Input
UBP Upper Byte Enable Input
LBP Lower Byte Enable Input
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M36L0R8060T1, M36L0R8060B1
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Value
Min Max
Unit
TA Ambient Operating Temperature
–25
85 °C
TBIAS
Temperature Under Bias
–25 85 °C
TSTG
Storage Temperature
–65 125 °C
TLEAD
Lead Temperature During Soldering
(1) °C
VIO Input or Output Voltage
–0.5
VDDQ + 0.3
V
VDDF, VDDQF,
VCCP
Core and Input/Output Supply Voltages
–0.2
2.45
V
VPPF
Flash Program Voltage
–0.2 12.6 V
IO Output Short Circuit Current
100 mA
tVPPFH
Time for VPPF at VPPFH
100 hours
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
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