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PDF K1S321615M Data sheet ( Hoja de datos )
| Número de pieza | K1S321615M | |
| Descripción | 2Mx16 bit Uni-Transistor Random Access Memory | |
| Fabricantes | Samsung semiconductor | |
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K1S321615M
Document Title
2Mx16 bit Uni-Transistor Random Access Memory
UtRAMwww.DataSheet4U.com
Revision History
Revision No. History
0.0 Initial Draft
- Design target
Draft Date
Remark
September 4, 2000 Advance
0.1 Revised
- Change package type from FBGA to TBGA.
February 9, 2001 Preliminary
- Improve operating current from 30mA to 25mA.
- Change input and output reference voltage from 1.1V to 1.5V at AC
test condition.
- Expand max operating voltage from 3.0V to 3.3V.
- Expand max operating temperature from 70°C to 85°C.
- Release speed from 70/85ns to 100ns.
- Release standby current form 170µA to 200µA.
- Add Power up timing diagram.
- Add AC characteristics for continuous write.
1.0 Finalize
March 30, 2001 Final
- Release standby current form 200µA to 250µA.
- Release deep power down current form 10µA to 20µA.
- Release tWC for continuous write operation from 100ns to 110ns.
- Release tCW for continuous write operation from 90ns to 100ns.
- Release tAW for continuous write operation from 90ns to 100ns.
- Release tBW for continuous write operation from 90ns to 100ns.
- Release tWP for continuous write operation from 90ns to 100ns.
2.0 Revised
- Add product list
April 16, 2001
Final
3.0 Revised
- Improve standby current from 250µA to 150µA.
May 28, 2001
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
- 1 - Revision 3.0
May 2001
1 page  
K1S321615M
UtRAMwww.DataSheet4U.com
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Test Input/Output Reference) Dout
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Z0=50Ω
Input and output reference voltage: 1.5V
Output load(See right): CL=50pF
* Include scope and jig capacitance
RL=50Ω
50pF*
VL=1.5V
AC CHARACTERISTICS(Vcc=2.7~3.3V, TA=-25 to 85°C)
Parameter List
Symbol
Speed Bins
100ns1)
100ns2)
Min Max Min Max
Read Cycle Time
tRC 100 - 100 -
Address Access Time
tAA - 100 - 100
Chip Select to Output
tCO - 100 - 100
Output Enable to Valid Output
tOE - 50 - 50
UB, LB Access Time
tBA - 100 - 100
Read
Chip Select to Low-Z Output
UB, LB Enable to Low-Z Output
tLZ 10 - 10 -
tBLZ 10 - 10 -
Output Enable to Low-Z Output
tOLZ 5 - 5 -
Chip Disable to High-Z Output
tHZ 0 25 0 25
UB, LB Disable to High-Z Output
tBHZ
0 25 0 25
Output Disable to High-Z Output
tOHZ
0 25 0 25
Output Hold from Address Change
tOH 5 - 5 -
Write Cycle Time
tWC 100 - 110 -
Chip Select to End of Write
tCW 80 - 100 -
Address Set-up Time
tAS 0 - 0 -
Address Valid to End of Write
tAW 80 - 100 -
Write
UB, LB Valid to End of Write
Write Pulse Width
tBW 80 - 100 -
tWP 70 - 100 -
Write Recovery Time
tWR 0 - 0 -
Write to Output High-Z
tWHZ
0 30 0 30
Data to Write Time Overlap
tDW 40 - 40 -
Data Hold from Write Time
tDH 0 - 0 -
End Write to Output Low-Z
tOW 5 - 5 -
1. The characteristics which is restricted for continuous write operation over 20 times, please refer to technical note.
2. The characteristics for continuous write operation.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
- 5 - Revision 3.0
May 2001
5 Page 
TECHNICAL
NOTE
TNAL0001
UtRAM USAGE AwNwwD.DaTtaIMSheIeNt4GU.com
UtRAM USAGE AND TIMING
INTRODUCTION
UtRAM is based on single-transistor DRAM cells. As with any
other DRAM, the data in these cells must be periodically
refreshed to prevent data loss. What makes the UtRAM unique
is that it offers a true SRAM style interface that hides all refresh
operations from the memory controller.
START WITH A DRAM TECHNOLOGY
The key to the UtRAM is its high speed and low power. This
speed comes from the use of many small blocks, often just
32Kbits each, to create UtRAM arrays. The small blocks have
short word lines with little capacitance, eliminating a major
source of operating current in conventional DRAM blocks.
Each independent macro-cell on a UtRAM device consists of a
number of these blocks. Each chip has one or more macro.
The address decoding logic is also fast. UtRAM perform a
complete read operation in every tRC, but UtRAM needs power
up sequence like a DRAM.
Power Up Sequence and Diagram
1. Apply power.
2. Maintain stable power for a minium 200µs with CS=high.
3. Issue read operation at least 2 times.
Power On
CS=VIH
CS=VIL, UB or/and LB=VIL
ZZ=VIH
Initial State
(Wait 200µs)
Active
Read Operation(2 times)
Figure 1.
CS
Over 4us
DESIGN ACHIEVES SRAM SPECIFIC
OPERATIONS
The UtRAM design works just like an SRAM, with no wait
states or other overhead for precharging or refreshing its inter-
nal DRAM cells. SAMSUNG Electronics(SAMSUNG) hides
these operations with advanced design. Precharging takes
place during every access, overlapped with the end of the cycle
and the decoding portion of the next cycle.
Hiding refresh is more difficult, Every row in every block must
be refreshed at least once during the refresh interval to prevent
data loss. SAMSUNG provides a internal refresh controller for
devices. When all accesses during a refresh interval are
directed to one macro-cell, as can happen in signal processing
applications, a more sophisticated approach is required to hide
refresh. The pseudo SRAM, sometimes used on these applica-
tions, which is required a memory controller that can hold off
accesses when a refresh operation is needed. SAMSUNG
unique qualitative advantage over these parts(in addition to
quantitative improvements in access speed and power con-
sumption) is that the UtRAM never needs to hold off accesses,
and indeed it has no hold off signal. The circuitry that gives
SAMSUNG this advantage is fairly simple but has not previ-
ously been disclosed.
AVOID TIMING
Following figures are show you a abonormal timing which is
not supported on UtRAM and their solution.
At read operation, if your system have a timing which sustain
invalid states over 4us at read mode like Figure 1. There are
some guide line for proper operation of UtRAM.
When your system have multiple invalid address signal shorter
than tRC on the timing which showed in Figure 1, UtRAM need
a normal read timing during that cycle(Figure 2) or toggle the
CS to h’ igh’about t’RC(’Figure 3).
WE Less than tRC
Address
Figure 2.
CS
Over 4us
Put on read operation every 4us
WE
Address
tRC
SRAM/NVM PLANNING
YOON-000831
SAMSUNG Electronics CO., LTD. reserves the right to change products or specifications without notice.
©2000 SAMSUNG Electronics CO., LTD.
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