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PDF IDT5V9888 Data sheet ( Hoja de datos )

Número de pieza IDT5V9888
Descripción 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
3.3V EEPROM
PROGRAMMABLE CLOCK
GENERATOR
INDUSTRIALTEMPERATURERANGE
www.DataSheet4U.com
IDT5V9888
FEATURES:
• Three internal PLLs
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges:
LVTTL: up to 200MHz
LVPECL/ LVDS: up to 500MHz
• Reference Crystal Input with programmable oscillator gain and
programmable linear load capacitance
Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation
capability
• I/O Standards:
Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual
switchover options
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TQFP and VFQFPN packages
DESCRIPTION:
The IDT5V9888 is a programmable clock generator intended for high
performance data-communications, telecommunications, consumer, and
networking applications. There are three internal PLLs, each individually
programmable, allowing for three unique non-integer-related frequencies.
The frequencies are generated from a single reference clock. The
reference clock can come from one of the two redundant clock inputs. A
glitchless automatic or manual switchover function allows any one of the
redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG
interfaces. The programming interface enables the device to be pro-
grammed when it is in normal operation or what is commonly known as in-
system programmable. An internal EEPROM allows the user to save and
restore the configuration of the device without having to reprogram it on
power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback
divider. This allows the user to generate three unique non-integer-related
frequencies. The PLL loop bandwidth is programmable to allow the user
to tailor the PLL response to the application. For instance, the user can tune
the PLL parameters to minimize jitter generation or to maximize jitter
attenuation. Spread spectrum generation and fractional divides are
allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the
six output banks are configurable to be LVTTL, LVPECL, or LVDS. The
other four output banks are LVTTL. The outputs are connected to the PLLs
via the switch matrix. The switch matrix allows the user to route the PLL
outputs to any output bank. This feature can be used to simplify and optimize
the board layout. In addition, each output's slew rate and enable/disable
function can be programmed.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
c 2007 Integrated Device Technology, Inc.
1
OCTOBER 2007
DSC 7044/13

1 page




IDT5V9888 pdf
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
PLL FEATURES AND DESCRIPTIONS
INDUSTRIALTEMPERATURERANGE
www.DataSheet4U.com
D0 Divider
VCO
M0 Multiplier
Spread
Spectrum
Modulation
PLL0 Block Diagram
D1 Divider
VCO
M1 Multiplier
Spread
Spectrum
Modulation
PLL1 Block Diagram
D2 Divider
VCO
M2 Multiplier
PLL2 Block Diagram
5

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IDT5V9888 arduino
IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
www.DataSheet4U.com
The spread spectrum parameters such as the modulation frequency and profile will not be enabled nor will it have any impact on the PLL output when the
PLL is programmed for fractional divide.
The following is an example of how to set the fractional divider.
Example
FIN = 20MHz, FOUT1 = 168.75MHz, FOUT2 = 350MHz
Solving for 350MHz using Eq.2 and Eq.3 with PLL0 and spread spectrum off,
350MHz = 20MHz * (M / D)
P*2
For better jitter performance, keep D as small as possible
350MHz * 2 = M = 35
20MHz P 1
Therefore, we have D = 1, M = 35 (N = 16, A = 2) for PLL0 with P = 1 on output bank4 resulting in 350MHz.
Solving for 168.75MHz with PLL1 and fractional divide enabled:
168.75MHz = 20MHz * (M / D)
P*2
168.75MHz * 2 = M = 16.875 or 33.75
20MHz P 1
2
The 33.75 value is chosen to achieve the highest VCO frequency possible. Next step is to figure out the setting for the fractional divide using Eq.3.
33.75 = 2*N + A + 1 + SS_OFFSET * 1/64
Integer value 33 can be determined by N and A, thus leaving 0.75 left to be solved.
2*N + A + 1 = 33
SS_OFFSET = 64 * 0.75 = 48
Therefore, we have D=1, M=33.75 (N=15, A=2, SS_OFFSET=48) for PLL1 with P=2 on an output bank resulting in 168.75MHz.
The fractional divider can be determined if it is needed by following the steps in the previous example. Note that the 5V9888 should not be programmed with
TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator. The A[3:0] must be used and set to be greater than '2' for
a more accurate fractional divide.
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