DataSheet.es    


PDF SC68C752B Data sheet ( Hoja de datos )

Número de pieza SC68C752B
Descripción 64-byte FIFOs and Motorola uP interface
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



Hay una vista previa y un enlace de descarga de SC68C752B (archivo pdf) en la parte inferior de esta página.


Total 49 Páginas

No Preview Available ! SC68C752B Hoja de datos, Descripción, Manual

SC68C752B
www.DataSheet4U.com
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte
FIFOs and Motorola µP interface
Rev. 03 — 29 November 2005
Product data sheet
1. General description
The SC68C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s.
The SC68C752B offers enhanced features. It has a Transmission Control Register (TCR)
that stores receiver FIFO threshold levels to start/stop transmission during hardware and
software flow control. With the FIFO Rdy register, the software gets the status of
TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user
with error indications, operational status, and modem interface control. System interrupts
may be tailored to meet user requirements. An internal loopback capability allows
on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and
receives characters on the RX signal. Characters can be programmed to be 5 bits, 6 bits,
7 bits, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be
programmed to interrupt at different trigger levels. The UART generates its own desired
baud rate based upon a programmable divisor and its input clock. It can transmit even,
odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing
errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The
UART also contains a software interface for modem control operations, and has software
flow control and hardware flow control capabilities.
The SC68C752B is available in LQFP48 and HVQFN32 packages.
2. Features
s Dual channel with Motorola µP interface
s Up to 5 Mbit/s data rate
s 64-byte transmit FIFO
s 64-byte receive FIFO with error flags
s Programmable and selectable transmit and receive FIFO trigger levels for DMA and
interrupt generation
s Software/hardware flow control
x Programmable Xon/Xoff characters
x Programmable Auto-RTS and Auto-CTS
s Optional data flow resume by Xon any character
s DMA signalling capability for both received and transmitted data
s Supports 5 V, 3.3 V and 2.5 V operation
s 5 V tolerant inputs
s Software selectable baud rate generator

1 page




SC68C752B pdf
Philips Semiconductors
SC68C752Bwww.DataSheet4U.com
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
5.2 Pin description
Table 2:
Symbol
A0
A1
A2
A3
Pin description
Pin Type
LQFP48 HVQFN32
28 19 I
27 18 I
26 17 I
11 9
I
CDA, CDB
40, 16
-
I
CS
10 8
I
CTSA, CTSB 38, 23
25, 15
I
D0 to D7
44, 45, 46, 27, 28, 29, I/O
47, 48, 1, 30, 31, 32,
2, 3 1, 2
DSRA, DSRB 39, 20
-
I
DTRA, DTRB 34, 35
-
O
GND
IRQ
17, 24
30
13
21
I
O
Description
Address 0 select bit. Internal registers address selection.
Address 1 select bit. Internal registers address selection.
Address 2 select bit. Internal registers address selection.
Address 3. A3 is used to select Channel A or Channel B. A logic LOW
selects Channel A, and a logic HIGH selects Channel B. (See Table 3.)
Carrier Detect (active LOW). These inputs are associated with
individual UART Channel A and Channel B. A logic LOW on these pins
indicates that a carrier has been detected by the modem for that
channel. The state of these inputs is reflected in the Modem Status
Register (MSR).
Chip Select (active LOW). This pin enables data transfers between the
user CPU and the SC68C752B for the channel(s) addressed. Individual
UART sections (A, B) are addressed by A3. See Table 3.
Clear to Send (active LOW). These inputs are associated with
individual UART Channel A and Channel B. A logic 0 (LOW) on the CTS
pins indicates the modem or data set is ready to accept transmit data
from the SC68C752B. Status can be tested by reading MSR[4]. These
pins only affect the transmit and receive operations when Auto-CTS
function is enabled via the Enhanced Feature Register EFR[7] for
hardware flow control operation.
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for
transferring information to or from the controlling CPU. D0 is the least
significant bit and the first data bit in a transmit or receive serial data
stream.
Data Set Ready (active LOW). These inputs are associated with
individual UART Channel A and Channel B. A logic 0 (LOW) on these
pins indicates the modem or data set is powered-on and is ready for data
exchange with the UART. The state of these inputs is reflected in the
Modem Status Register (MSR).
Data Terminal Ready (active LOW). These outputs are associated with
individual UART Channel A and Channel B. A logic 0 (LOW) on these
pins indicates that the SC68C752B is powered-on and ready. These pins
can be controlled via the Modem Control Register. Writing a logic 1 to
MCR[0] will set the DTR output to logic 0 (LOW), enabling the modem.
The output of these pins will be a logic 1 after writing a logic 0 to MCR[0],
or after a reset.
Signal and power ground.
Interrupt Request. Interrupts from UART Channel A and Channel B are
wire-ORed internally to function as a single IRQ interrupt. This pin
transitions to a logic 0 (if enabled by the Interrupt Enable Register)
whenever a UART channel(s) requires service. Individual channel
interrupt status can be determined by addressing each channel through
its associated internal register, using CS and A3. An external pull-up
resistor must be connected between this pin and VCC.
SC68C752B_3
Product data sheet
Rev. 03 — 29 November 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 49

5 Page





SC68C752B arduino
Philips Semiconductors
SC68C752Bwww.DataSheet4U.com
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
There are two other enhanced features relating to software flow control:
Xon Any function (MCR[5]): Operation will resume after receiving any character
after recognizing the Xoff character. It is possible that an Xon1 character is
recognized as an Xon Any character, which could cause an Xon2 character to be
written to the RX FIFO.
Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the
RX FIFO.
6.3.1 Receive flow control
When software flow control operation is enabled, the SC68C752B will compare incoming
data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be
received sequentially). When the correct Xoff character are received, transmission is
halted after completing transmission of the current character. Xoff detection also sets
IIR[4] (if enabled via IER[5]) and causes IRQ to go HIGH.
To resume transmission, an Xon1/Xon2 character must be received (in certain cases
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.
6.3.2 Transmit flow control
Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level
programmed in TCR[3:0].
Xon1/Xon2 character is transmitted when the RX FIFO reaches the RESUME trigger level
programmed in TCR[7:4].
The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an
ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7
characters, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2, Xon1/Xon2 will be
transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but
this functionality is included to maintain compatibility with earlier designs.)
It is assumed that software flow control and hardware flow control will never be enabled
simultaneously. Figure 7 shows an example of software flow control.
SC68C752B_3
Product data sheet
Rev. 03 — 29 November 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 49

11 Page







PáginasTotal 49 Páginas
PDF Descargar[ Datasheet SC68C752B.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
SC68C752B64-byte FIFOs and Motorola uP interfaceNXP Semiconductors
NXP Semiconductors

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar