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PDF M69KB096AB Data sheet ( Hoja de datos )

Número de pieza M69KB096AB
Descripción 64 Mbit (4Mb x 16)/ 104MHz Clock Rate 1.8V Supply - Bare Die Burst PSRAM
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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M69KB096AB
64 Mbit (4 Mb x16), 104MHz Clock Rate,
1.8V Supply, Bare Die, Burst PSRAM
PRELIMINARY DATA
Features summary
Supply Voltage
– VCC = 1.7 to 1.95V core supply voltage
– VCCQ = 1.7 to 1.95V for I/O buffers
User-selectable Operating Modes
– Asynchronous Modes: Random Read, and
Write, Page Read
– Synchronous Modes: NOR-Flash, Full
Synchronous (Burst Read and Write)
Asynchronous Random Read
– Access Time: 70ns
Asynchronous Page Read
– Page Size: 4, 8 or 16 Words
– Subsequent Read Within Page: 20ns
Burst Read
– Fixed Length (4, 8, 16 or 32 Words) or
Continuous
– Maximum Clock Frequency: 104MHz
– Output delay: 7ns at 104MHz
Low Power Consumption
– Active Current: < 25mA
– Standby Current: 140µA
– Deep Power-Down Current: < 10µA
Low Power Features
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) Mode
– Automatic Temperature-compensated Self-
Refresh
Operating Temperature
– –30°C to +85°C
Wafer
The M69KB096AB is only available as part of a multi-chip package Product.
November 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Rev 1
1/73
www.st.com
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M69KB096AB pdf
M69KB096AB
List of tables
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Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Mode Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standard Asynchronous Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Frequency versus Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Asynchronous Write Operations (NOR-Flash Synchronous Mode) . . . . . . . . . . . . . . . . . . 22
Synchronous Read Operations (NOR-Flash Synchronous Mode) . . . . . . . . . . . . . . . . . . . 22
Full Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Register Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Refresh Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Device ID Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Asynchronous Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Asynchronous Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Clock Related AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Synchronous Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Power-Up and Deep Power-Down AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Bond Pad Location and Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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M69KB096AB arduino
M69KB096AB
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2.8 Lower Byte Enable (LB)
The Lower Byte Enable, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7)
to or from the lower part of the selected address during a write or read operation.
If both LB and UB are disabled (High), the device will disable the data bus from receiving or
transmitting data. Although the device will seem to be deselected, it remains in an active mode
as long as E remains Low.
2.9 Clock Input (K)
The Clock, K, is an input signal to synchronize the memory to the microcontroller or system bus
frequency during Synchronous Burst Read and Write operations. The Clock input signal
increments the device internal address counter.
The addresses are latched on the rising edge of the Clock K, when L is Low during
Synchronous Bus operations.
Latency counts are defined from the first Clock rising edge after L falling edge to the first data
input latched or the first data output valid.
The Clock input is required during all synchronous operations and must be kept Low during
asynchronous operations.
2.10 Configuration Register Enable (CR)
When this signal is driven High, VIH, bus read or write operations access either the value of the
Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR) according to
the value of A19.
2.11 Latch Enable (L)
In Synchronous mode, addresses are latched on the rising edge of the Clock K when the Latch
Enable input, L is Low. In Asynchronous mode, addresses are latched on L rising edge.
2.12 Wait (WAIT)
The WAIT output signal provides data-valid feedback during Synchronous Burst Read and
Write operations. The signal is gated by E. Driving E High while WAIT is asserted may cause
data corruption.
Once a read or write operation has been initiated, the WAIT signal goes active to indicate that
the M69KB096AB device requires additional time before data can be transferred.
The WAIT signal also is used for arbitration when a Read or Write operation is launched while
an on-chip refresh is in progress (see Figure 6: Refresh Collision during Synchronous Burst
Read in Variable Latency Mode).
Typically, the WAIT pin of the M69KB096AB can be connected to a shared WAIT signal used by
the processor to coordinate transactions with multiple memories on the synchronous bus.
See Section 3: Power-up for details on the WAIT signal operation.
11/73

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