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PDF SC2615 Data sheet ( Hoja de datos )
| Número de pieza | SC2615 | |
| Descripción | Complete DDR Power Solution | |
| Fabricantes | Semtech | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SC2615 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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POWER MANAGEMENT
Description
The SC2615 is a fully integrated, Three in One, Linear
DDR power solution providing power for the VDDQ and
the VTT rails. The SC2615 completely adheres to the
ACPI sleep state power requirements per IntelR
motherboard specifications. A linear regulator controller
provides the high current of the VDDQ during S0, via an
external Power MOSFET, while an internal 1.8A (min) sink/
source regulator supplies the termination voltage.
In addition to these two blocks, an Internal LDO provides
VDDQ power during S3, capable of sourcing 650 mA.
The SC2615 uses IntelR defined Latched BF_CUT signal
which is also used to drive the external Blocking MOSFET.
Additional logic, two UVLOs and three thermal shutdown
circuits assure reliability of this single chip DDR power
solution. A Power Good Output indicates the rails are in
regulation.
A Soft Start/Enable pin assures proper startup and allows
external shutdown control. The MLP package provides
excellent thermal impedance while keeping a small
footprint.
Typical Application Circuit
SC2615
Complete DDR Power Solution
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Features
Single chip solution adheres to ACPI sleep state
requirements using BF_CUT
UVLO on 3.3V and 12V
Internal S3 state LDO for VDDQ supplies 650 mA
Dual thermal shutdown
Fast transient response
Internal VTT regulator Sinks and Sources 1.8A
(Min)
Power good output
18 pin MLP package
Applications
DDR power solution for IntelR motherboard
applications
High speed data line termination
Graphic cards
Disk drives
12V
5V
5V STBY
1uF
BF_CUT
PWRGD
BF_CUT
PWRGD
0.1uF
Cin
SC2615
16 12VCC
3.3VCC 9
4 5VSBY
TG 15
11 BF_CUT
NC 14
10 PGOOD
NC 13
18 SS/EN VDDQSTBY 7
17 NC
VDDQIN 8
12 AGND
FB 1
3 LGND
VTT 6
2 VTTSNS
VTT 5
Cout
VDDQ
VTT
Revision 2, April 2003
1
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1 page  
POWER MANAGEMENT
Block Diagram
SC2615
www.DataSheet4U.com
2003 Semtech Corp.
5
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5 Page 
SC2615
POWER MANAGEMENT
Mounting Considerations
Description
Solder Mask
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The MLP18 is a leadless package whose electrical
connections are made by lands on the bottom surface
of the component. These lands are soldered directly to
the PC board. The MLP has an exposed die attach pad,
which enhances the thermal and electrical characteristics
enabling high power applications. Power handling capability
of the MLP package is typically >2x the power of other
SMT packages. In order to take full advantage of this
feature the exposed pad must be physically connected
to the PCB substrate with solder.
Thermal Pad Via Design
Thermal data (θja) for the MLP18 is based on a 4 layer
PCB incorporating vias which act as the thermal path to
other layers. (Ref: Jedec Specification JESD 51-5). Based
on thermal performance, four-layer PCB’s with vias are
recommended to effectively remove heat from the device.
Vias should be 0.3mm diameter on a 1.2mm pitch, and
should be plugged to prevent voids being formed between
the exposed pad and PCB thermal pad due to solder
escaping by capillary action. Plugging can be accomplished
by “tenting” the via during the solder mask process. The
via solder mask diameter should be 100µm larger than
the via diameter.
Two layer boards have no vias, thus any heat sinking must
be accomplished in the same plane as the metal traces.
This will typically require an increase in the PC board area.
Design the solder mask around all pads on each side,
i.e. there should be no solder mask between adjacent
terminal fingers.
Exposed Pad Stencil Design
It is good practice to minimize the presence of voids within
the exposed pad inter-connection. Total elimination is
difficult but the design of the exposed pad stencil is
important, a single slotted rectangular pattern is
recommended. (If large exposed pads are screened with
excessive solder, the device may “float”, thus causing a
gap between the MLP terminal and the PCB land
metalization.) The proposed stencil designs enables out-
gassing of the solder paste during reflow as well as
controlling the finished solder thickness.
2003 Semtech Corp.
11
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11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet SC2615.PDF ] | |
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