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PDF GS8162V72CC-333 Data sheet ( Hoja de datos )
| Número de pieza | GS8162V72CC-333 | |
| Descripción | 256K x 72 18Mb S/DCD Sync Burst SRAMs | |
| Fabricantes | GSI Technology | |
| Logotipo |  |
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Preliminary
GS8162V72CCw-3w3w3.D/3at0a0Sh/2ee5t04U/2.c0o0m/150
209-Bump BGA
Commercial Temp
Industrial Temp
256K x 72
18Mb S/DCD Sync Burst SRAMs
333 MHz–150 MHz
1.8 V VDD
1.8 V I/O
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 1.8 V +10%/–10% core power supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 209-bump BGA package
• Pb-Free 209-bump BGA package available
Functional Description
Applications
The GS8162V72CC is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although of a
type originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main store to
networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode . Holding the FT mode pin low places the RAM in
Flow Through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS8162V72CC is an SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs
pipeline disable commands to the same degree as read commands.
SCD SRAMs pipeline deselect commands one stage less than read
commands. SCD RAMs begin turning off their outputs immediately
after the deselect command has been captured in the input registers.
DCD RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge of
clock. The user may configure this SRAM for either mode of
operation using the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low) for
multi-drop bus applications and normal drive strength (ZQ floating or
high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS8162V72CC operates on a 1.8 V power supply. All input are
1.8 V compatible. Separate output power (VDDQ) pins are used to
decouple output noise from the internal circuits and are 1.8 V
compatible.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
tKQ
tCycle
Curr
tKQ
tCycle
Curr
Parameter Synopsis
-333 -300 -250 -200 -150 Unit
2.8 2.8 3.0 3.0 3.8 ns
3.0 3.3 4.0 5.0 6.7 ns
545 495 425 345 270 mA
4.5 5.0 5.5 6.5 7.5 ns
4.5 5.0 5.5 6.5 7.5 ns
380 345 315 275 250 mA
Rev: 1.01 2/2005
1/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
1 page  
Preliminary
GS8162V72CCw-3w3w3.D/3at0a0Sh/2ee5t04U/2.c0o0m/150
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO L
H
Linear Burst
Interleaved Burst
Power Down Control
L or NC
ZZ
H
Active
Standby, IDD = ISB
Single/Dual Cycle Deselect Control
L
SCD H or NC
Dual Cycle Deselect
Single Cycle Deselect
FLXDrive Output Impedance Control
ZQ
L
H or NC
High Drive (Low Impedance)
Low Drive (High Impedance)
Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.01 2/2005
5/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
5 Page 
Preliminary
GS8162V72CCw-3w3w3.D/3at0a0Sh/2ee5t04U/2.c0o0m/150
Logic Levels
Parameter
Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage
VIH 0.6*VDD — VDD + 0.3 V
1
VDD Input Low Voltage
VIL
–0.3
— 0.3*VDD
V
1
VDDQ I/O Input High Voltage
VIHQ 0.6*VDD
— VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
VILQ –0.3
— 0.3*VDD
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Undershoot Measurement and Timing
VIH
VSS
50%
VSS – 2.0 V
20% tKC
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Symbol
Input Capacitance
Input/Output Capacitance
Note:
These parameters are sample tested.
CIN
CI/O
Overshoot Measurement and Timing
VDD + 2.0 V
50%
20% tKC
VDD
VIL
Test conditions
VIN = 0 V
VOUT = 0 V
Typ. Max. Unit
4 5 pF
6 7 pF
Rev: 1.01 2/2005
11/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
11 Page | ||
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