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PDF SC16C754B Data sheet ( Hoja de datos )
| Número de pieza | SC16C754B | |
| Descripción | 5 V - 3.3 V and 2.5 V quad UART - 5 Mbit/s (max.) | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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SC16C754B
www.DataSheet4U.com
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte
FIFOs
Rev. 04 — 6 October 2008
Product data sheet
1. General description
The SC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s
(3.3 V and 5 V). The SC16C754B offers enhanced features. It has a Transmission Control
Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during
hardware and software flow control. With the FIFO Ready (FIFO Rdy) register, the
software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status
registers provide the user with error indications, operational status, and modem interface
control. System interrupts may be tailored to meet user requirements. An internal
loopback capability allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or
8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed
to interrupt at different trigger levels. The UART generates its own desired baud rate
based upon a programmable divisor and its input clock. It can transmit even, odd, or no
parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors,
FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART
also contains a software interface for modem control operations, and has software flow
control and hardware flow control capabilities.
The SC16C754B is available in plastic LQFP64, LQFP80 and PLCC68 packages.
2. Features
I 4 channel UART
I 5 V, 3.3 V and 2.5 V operation
I Pin compatible with SC16C654IA68, TL16C754, and SC16C554IA68 with additional
enhancements, and software compatible with TL16C754
I Up to 5 Mbit/s data rate (at 3.3 V and 5 V; at 2.5 V maximum data rate is 3 Mbit/s)
I 5 V tolerant on input only pins1
I 64-byte transmit FIFO
I 64-byte receive FIFO with error flags
I Industrial temperature range (−40 °C to +85 °C)
I Programmable and selectable transmit and receive FIFO trigger levels for DMA and
interrupt generation
1. For data bus pins D7 to D0, see Table 24 “Limiting values”.
1 page  
NXP Semiconductors
SC16C754Bwww.DataSheet4U.com
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
n.c. 1
n.c. 2
DSRA 3
CTSA 4
DTRA 5
VCC 6
RTSA 7
INTA 8
CSA 9
TXA 10
IOW 11
TXB 12
CSB 13
INTB 14
RTSB 15
GND 16
DTRB 17
CTSB 18
DSRB 19
n.c. 20
SC16C754BIB80
Fig 3. Pin configuration for LQFP80
60 n.c.
59 DSRD
58 CTSD
57 DTRD
56 GND
55 RTSD
54 INTD
53 CSD
52 TXD
51 IOR
50 TXC
49 CSC
48 INTC
47 RTSC
46 VCC
45 DTRC
44 CTSC
43 DSRC
42 n.c.
41 n.c.
002aaa867
SC16C754B_4
Product data sheet
Rev. 04 — 6 October 2008
© NXP B.V. 2008. All rights reserved.
5 of 51
5 Page 
NXP Semiconductors
SC16C754Bwww.DataSheet4U.com
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.2.1 Auto-RTS
Auto-RTS data flow control originates in the receiver block (see Figure 1 “Block diagram of
SC16C754B”). Figure 6 shows RTS functional timing. The receiver FIFO trigger levels
used in auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the
halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is
de-asserted. The sending device (for example, another UART) may send an additional
byte after the trigger level is reached (assuming the sending UART has another byte to
send) because it may not recognize the de-assertion of RTS until it has begun sending the
additional byte. RTS is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This re-assertion allows the sending
device to resume transmission.
RX
RTS
Start byte N Stop
Start byte N + 1 Stop
Start
IOR
12
N N+1
002aaa226
Fig 6.
N = receiver FIFO trigger level.
The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1.
RTS functional timing
6.2.2 Auto-CTS
The transmitter circuitry checks CTS before sending the next data byte. When CTS is
active, the transmitter sends the next byte. To stop the transmitter from sending the
following byte, CTS must be de-asserted before the middle of the last stop bit that is
currently being sent. The auto-CTS function reduces interrupts to the host system. When
flow control is enabled, CTS level changes do not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends
any data present in the transmit FIFO and a receiver overrun error may result.
TX Start byte 0 to 7 Stop
Start byte 0 to 7 Stop
CTS
002aaa227
Fig 7.
When CTS is LOW, the transmitter keeps sending serial data out.
When CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter
finishes sending the current byte, but it does not send the next byte.
When CTS goes from HIGH to LOW, the transmitter begins sending data again.
CTS functional timing
SC16C754B_4
Product data sheet
Rev. 04 — 6 October 2008
© NXP B.V. 2008. All rights reserved.
11 of 51
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| PDF Descargar | [ Datasheet SC16C754B.PDF ] | |
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