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PDF RD74VT1G04 Data sheet ( Hoja de datos )

Número de pieza RD74VT1G04
Descripción Single Inverter Buffer / Dual Supply Voltage Translator
Fabricantes Renesas Technology 
Logotipo Renesas Technology Logotipo



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RD74VT1G04
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Single Inverter Buffer / Dual Supply Voltage Translator
Description
REJ03D0514–0100
Rev.1.00
Mar. 29, 2005
The RD74VT1G04 has an inverter in a 6-pin package. The input is designed to track VCCIN, which accepts voltage
from 1.2 V to 3.6 V, and the output is designed to track VCCOUT, which operates at 1.2 V to 3.6 V. Low voltage and
high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.
Features
This product function as level shift that change VCCIN input level to VCCOUT output level by providing different
supply voltage to VCCIN and VCCOUT.
Supplied on emboss taping for high-speed automatic mounting.
The basic gate function is lined up as Renesas uni logic series.
Supply voltage range: VCCIN = 1.2 V to 3.6 V
VCCOUT = 1.2 V to 3.6 V
Operating temperature range: –40 to +85°C
All inputs: VIH (Max.) = 3.6 V (@VCCIN = 0 V to 3.6 V)
All outputs: VO (Max.) = 3.6 V (@VCCOUT = 0 V)
Output current:
±2 mA (@VCCOUT = 1.2 V)
±4 mA (@VCCOUT = 1.4 V to 1.6 V)
±6 mA (@VCCOUT = 1.65 V to 1.95 V)
±18 mA (@VCCOUT = 2.3 V to 2.7 V)
±24 mA (@VCCOUT = 3.0 V to 3.6 V)
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
RD74VT1G04CLE
WCSP-6 pin
SXBG0006KB–A
(TBS-6AV)
CL E (3,000 pcs/reel)
Article Indication
Marking
Year code
V5YM
Month code
Rev.1.00 Mar. 29, 2005 page 1 of 1

1 page




RD74VT1G04 pdf
RD74VT1G04
Switching Characteristics (Cont.)
www.DataSheet4U.com
Item
FROM
Symbol (Input)
Propagation
delay time
tPLH
tPHL
A
TO
(Output)
Y
VCCOUT=
1.2V
Typ
9.2
9.2
VCCIN = 2.5 ± 0.2 V
Ta = –40 to 85°C
VCCOUT=
1.5±0.1V
VCCOUT=
1.8±0.15V
VCCOUT=
2.5±0.2V
VCCOUT=
3.3±0.3V
Test
Min Max Min Max Min Max Min Max Unit Conditions
2.0 8.8 1.5 5.7 1.0 4.3 1.0 3.9 ns CL = 15 pF
2.0 8.8 1.5 5.7 1.0 4.3 1.0 3.9
RL = 2.0 k
Item
FROM
Symbol (Input)
Propagation
delay time
tPLH
tPHL
A
TO
(Output)
Y
VCCOUT=
1.2V
Typ
9.5
9.5
Ta = –40 to 85°C
VCCIN = 1.8 ± 0.15 V
VCCOUT=
1.5±0.1V
VCCOUT=
1.8±0.15V
VCCOUT=
2.5±0.2V
VCCOUT=
3.3±0.3V
Test
Min Max Min Max Min Max Min Max Unit Conditions
2.0 9.2 1.5 6.0 1.0 4.7 1.0 4.3 ns CL = 15 pF
2.0 9.2 1.5 6.0 1.0 4.7 1.0 4.3
RL = 2.0 k
Item
FROM
Symbol (Input)
Propagation
delay time
tPLH
tPHL
A
TO
(Output)
Y
VCCOUT=
1.2V
Typ
9.5
9.5
VCCIN = 1.5 ± 0.1 V
Ta = –40 to 85°C
VCCOUT=
1.5±0.1V
VCCOUT=
1.8±0.15V
VCCOUT=
2.5±0.2V
VCCOUT=
3.3±0.3V
Test
Min Max Min Max Min Max Min Max Unit Conditions
2.0 9.7 1.5 6.8 1.0 5.2 1.0 5.0 ns CL = 15 pF
2.0 9.7 1.5 6.8 1.0 5.2 1.0 5.0
RL = 2.0 k
Item
Propagation
delay time
Symbol
tPLH
tPHL
FROM
(Input)
A
TO
(Output)
Y
VCCOUT=
1.2V
Typ
10.5
10.5
Ta = –40 to 85°C
VCCOUT=
1.5±0.1V
VCCOUT=
1.8±0.15V
VCCOUT=
2.5±0.2V
Typ Typ Typ
7.5 5.9 4.4
7.5 5.9 4.4
VCCIN = 1.2 V
VCCOUT=
3.3±0.3V
Typ
4.2
4.2
Test
Unit Conditions
ns CL = 15 pF
RL = 2.0 k
Operating Characteristics
Item
Power dissipation
capacitance
Symbol
CPD
VCCIN (V)
3.3
VCCOUT (V)
3.3
Ta = 25°C
Min Typ Max
— 12 —
Unit
pF
Test Conditions
f = 10 MHz
CL = 0
Power-up Considerations
Level-translation devices offer an opportunity for successful mixed-voltage signal design.
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations,
or other anomalies caused by improperly biased device pins.
Take these precautions to guard against such power-up problems.
1. Connect ground before any supply voltage is applied.
2. Next, Power up the input side of the device.
(Power up of VCCIN is first, Next power up is VCCOUT)
Rev.1.00 Mar. 29, 2005 page 5 of 7

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