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PDF SC16C554DB Data sheet ( Hoja de datos )

Número de pieza SC16C554DB
Descripción 5 V 3.3 V and 2.5 V quad UART - 5 Mbit/s (max.) with 16-byte FIFOs
Fabricantes NXP Semiconductors 
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No Preview Available ! SC16C554DB Hoja de datos, Descripción, Manual

SC16C554B/554DB
www.DataSheet4U.com
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte
FIFOs
Rev. 01 — 9 February 2005
Product data sheet
1. General description
The SC16C554B/554DB is a 4-channel Universal Asynchronous Receiver and
Transmitter (QUART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. It comes with an Intel® or Motorola® interface.
The SC16C554B/554DB is pin compatible with the ST16C554 and TL16C554 and it will
power-up to be functionally equivalent to the 16C454. Programming of control registers
enables the added features of the SC16C554B/554DB. Some of these added features are
the 16-byte receive and transmit FIFOs, four receive trigger levels. The
SC16C554B/554DB also provides DMA mode data transfers through FIFO trigger levels
and the TXRDY and RXRDY signals. On-board status registers provide the user with error
indications, operational status, and modem interface control. System interrupts may be
tailored to meet user requirements. An internal loop-back capability allows on-board
diagnostics.
The SC16C554B/554DB operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic PLCC68, LQFP64, and LQFP80 packages.
2. Features
s 4 channel UART
s 5 V, 3.3 V and 2.5 V operation
s Industrial temperature range (40 °C to +85 °C)
s The SC16C554B is pin and software compatible with the industry-standard
ST16C454/554, ST68C454/554, ST16C554, TL16C554
s The SC16C554DB is pin and software compatible with ST16C554D, and software
compatible with ST16C454/554, ST16C554, TL16C554
s Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
s 5 V tolerant inputs
s 16-byte transmit FIFO
s 16-byte receive FIFO with error flags
s Programmable auto-RTS and auto-CTS
x In auto-CTS mode, CTS controls transmitter
x In auto-RTS mode, RxFIFO contents and threshold control RTS
s Automatic hardware flow control (RTS/CTS)
s Software selectable Baud Rate Generator
s Four selectable Receive FIFO interrupt trigger levels
s Standard modem interface

1 page




SC16C554DB pdf
Philips Semiconductors
SC16C554B/554DBwww.DataSheet4U.com
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
5. Pinning information
5.1 Pinning
5.1.1 PLCC68
DSRA 10
CTSA 11
DTRA 12
VCC 13
RTSA 14
INTA 15
CSA 16
TXA 17
IOW 18
TXB 19
CSB 20
INTB 21
RTSB 22
GND 23
DTRB 24
CTSB 25
DSRB 26
SC16C554DBIA68
16 mode
Fig 3. Pin configuration for PLCC68 (16 mode)
60 DSRD
59 CTSD
58 DTRD
57 GND
56 RTSD
55 INTD
54 CSD
53 TXD
52 IOR
51 TXC
50 CSC
49 INTC
48 RTSC
47 VCC
46 DTRC
45 CTSC
44 DSRC
002aaa879
9397 750 13133
Product data sheet
Rev. 01 — 9 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 51

5 Page





SC16C554DB arduino
Philips Semiconductors
SC16C554B/554DBwww.DataSheet4U.com
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Table 2:
Symbol
IOW
Pin description …continued
Pin
Type
PLCC68 LQFP64 LQFP80
18 9
31 I
IRQ
15 -
-O
n.c. 21, 49, -
52, 54,
55, 65
RESET
(RESET)
37
27
1, 10,
20, 21,
30, 40,
41, 49,
52, 60,
61, 71,
80
53
-
I
RIA, RIB,
RIC, RID
8, 28,
42, 62
63, 19, 18, 43, I
30, 50 58, 3
RTSA, RTSB, 14, 22, 5, 13, 26, 35, O
RTSC, RTSD 48, 56 36, 44 66, 75
R/W
18 -
-I
Description
Input/Output Write strobe (active LOW). This function is
associated with the 16 mode only. A logic 0 transition on this pin will
transfer the contents of the data bus (D0 to D7) from the external
CPU to an internal register that is defined by address bits A0 to A2.
When the 68 mode is selected, this pin functions as R/W (see
definition under R/W).
Interrupt Request or Interrupt ‘A’. This function is associated with
the 68 mode only. In the 68 mode, interrupts from UART channels
A to D are wire-ORed internally to function as a single IRQ
interrupt. This pin transitions to a logic 0 (if enabled by the interrupt
enable register) whenever a UART channel(s) requires service.
Individual channel interrupt status can be determined by addressing
each channel through its associated internal register, using CS and
A3 to A4. In the 68 mode, and external pull-up resistor must be
connected between this pin and VCC. The function of this pin
changes to INTA when operating in the 16 mode (see definition
under INTA).
not connected
Reset. In the 16 mode, a logic 1 on this pin will reset the internal
registers and all the outputs. The UART transmitter output and the
receiver input will be disabled during reset time. (See Section 7.10
“SC16C554B/554DB external reset conditions” for initialization
details.) When 16/68 is a logic 0 (68 mode), this pin functions
similarly, bus as an inverted reset interface signal, RESET.
Ring Indicator (active LOW). These inputs are associated with
individual UART channels, A to D. A logic 0 on this pin indicates the
modem has received a ringing signal from the telephone line. A
logic 1 transition on this input pin will generate an interrupt.
Request to Send (active LOW). These outputs are associated with
individual UART channels, A to D. A logic 0 on the RTS pin
indicates the transmitter has data ready and waiting to send. Writing
a logic 1 in the modem control register MCR[1] will set this pin to a
logic 0, indicating data is available. After a reset this pin will be set
to a logic 1. This pin only affects the transmit and receive operations
when auto-RTS function is enabled via MCR[5] for hardware flow
control operation.
Read/Write strobe. This function is associated with the 68 mode
only. This pin provides the combined functions for Read or Write
strobes.
Logic 1 = Read from UART register selected by CS and A0 to A4.
Logic 0 = Write to UART register selected by CS and A0 to A4.
9397 750 13133
Product data sheet
Rev. 01 — 9 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 51

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