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PDF LC82220 Data sheet ( Hoja de datos )
| Número de pieza | LC82220 | |
| Descripción | Motion JPEG Decoder LSI | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LC82220 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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Ordering number : EN*5422
CMOS LSI
LC82220
Motion JPEG Decoder LSI
Preliminaly
Overview
The LC82220 is a single-chip JPEG decoder designed for
wide range of digital video playback applications
including amusement systems, video games and PC JPEG
playback cards. The LC82220 is capable of decoding
JPEG bitstreams of SIF resolution with a picture rate of 30
frames/sec. The digital video output can be formatted for
NTSC, PAL, SECAM, or any other optional video
standard. The complete decoding function is realised with
the LC82220, a standard 8-bit or 16-bit microcontroller
and a bank of DRAM. A typical memory configuration is
a single 128 k × 16 or 256 k × 16 DRAM. The LC82220
also supports efficient video display functions such as
scroll and overlay.
Functions
• Support for JPEG format
• Real-time decoding of motion-JPEG with rate of 30
frames/sec
• Lowest solution cost for amusement, game, PC
systems
• Support for YUV 4:1:1 color format
• YUV or RGB digital video outputs compatible with
optional video format
• Programmable picture and display window format
• Support for trick display: scrolling, overlaying
• Standard 8/16-bit microcontroller interface with DMA
support for compressed data input
• Support SOI and EOI markers
• Direct connect to video DAC
• Direct connect to 2 M or 4 M DRAM as bit and frame
buffers
• Two Q-tables included
• High-speed processing by fixed Huffman tables
Package Dimensions
unit: mm
3182-QFP128E
[LC82220]
SANYO: QIP128E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
62096HA (OT) No. 5422-1/6
1 page  
LC82220
Continued from preceding page.
Pin No.
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Symbol
VSS
VDD
MD3
MD2
MD1
MD0
VSS
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
VSS
I/O
Ground
+5 V power supply
I/O
I/O Frame memory interface data bus
I/O
I/O
Ground
O
O
O
O
O Frame memory address signals
O
O
O
O
Ground
Function
System Configuration Example
1. Separate code bus type
This is a system in which the code and system busses are separated. The coded data input does not load down the
system bus.
No. 5422-5/6
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet LC82220.PDF ] | |
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