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PDF LC8220 Data sheet ( Hoja de datos )
| Número de pieza | LC8220 | |
| Descripción | JPEG Still Color Image Compression/Decompression LSI | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LC8220 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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Ordering number : EN*4909A
Preliminaly
CMOS LSI
LC8220
JPEG Still Color Image
Compression/Decompression LSI
Overview
The LC8220 JPEG LSI implements digital still image
compression and decompression conforming to the JPEG
(Joint Photographic Expert Group) standard. The LC8220
includes the baseline system of the ISO 10918 (JPEG)
standard, and requires no external components to construct
an application that performs JPEG compliant
compression/decompression.
Features
• Conforms to the ISO 10918-1 baseline system
• Four quantization tables and four Huffman tables (two
for AC and two for DC) are built in.
• Hardware support for JPEG marker codes
• Built-in bidirectional YUV - RGB converter
• Many color component sampling ratios are supported.
(e.g., YUV 4:1:1 and YMCK 1:1:1:1, etc.)
• Level shift function that can be defined for each
component
• Built-in dual buffers for reduced data transfer load
• Bus sizing function that allows direct connection to 8-,
16-, and 32-bit busses
• Endian control function
• Three independent data buses
Package Dimensions
unit: mm
3153A-QFP160
[LC8220]
SANYO: QFP160
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
32896HA (OT)/D1694TH (OT) No. 4909-1/13
1 page  
LC8220
Continued from preceding page.
Pin No.
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Symbol
VDD
VSS
PXD7
PXD6
PXD5
PXD4
PXD3
PXD2
PXD1
PXD0
VDD
VSS
PXSIZE0
PXSIZE1
(NC)
CDCS
CDRD
CDWR
CDRDY
CDINT
CDRLS
CDEND
CDFLSH
(NC)
(NC)
(NC)
(NC)
(NC)
CPUCD
CDSIZE
VDD
VSS
CDD15
CDD14
CDD13
CDD12
CDD11
CDD10
CDD9
CDD8
VDD
VSS
CDD7
CDD6
CDD5
CDD4
CDD3
CDD2
CDD1
CDD0
VDD
I/O Function
— +5 V power supply
— Ground
I/O
I/O
I/O
I/O Pixel data bus
I/O
I/O
I/O
I/O
— +5 V power supply
— Ground
I Bus width selection for the pixel bus
I (PXSIZE [1,0] = 00: 8 bits, 01: 16 bits, 1*: 32 bits)
—
I Code bus chip select*2
I Code bus read request*3
I Code bus write request*4
O Code bus ready for read/write requests*5
O Code bus interrupt request
I Code bus interrupt release
O Code bus last data output
I Code bus forcible buffer flush
—
—
—
—
—
I Connected CPU type setting for the code bus*1
I Bus width setting for the code bus (0: 8 bits, 1: 16 bits)
— +5 V power supply
— Ground
I/O
I/O
I/O
I/O
Code data bus (D15 to D8 are unused if an 8-bit CPU is used.*7)
I/O
I/O
I/O
I/O
— +5 V power supply
— Ground
I/O
I/O
I/O
I/O
Code data bus
I/O
I/O
I/O
I/O
— +5 V power supply
Note 1, 2, 3, 4, 5: These items are related to the CPU type.
6: Connect to VSS (ground).
7: Must be pulled up.
8: These are NC pins.
9: Connect to VDD.
Z**CS2
8086 family CPU (CPU = 1) CS
68000 family CPU (CPU = 0) AS
Z**RD3
RD
R/W
Z**WR4 Z**RDY5
WR RDY
DS ACK
No. 4909-5/13
5 Page 
Control Bus Interface Timing
Control Bus Read Cycle
LC8220
Control Bus Register Read Cycle (type 1)
Control Bus Register Read Cycle (type 2)
Item
t1 Read signal assert setup time (referenced to CLK)
t2 Read signal assert hold time (referenced to CLK)
t3 Chip select stabilization time (referenced to the read signal)
t4 Chip select hold time (referenced to the read signal)
t5 Address stabilization time (referenced to the read signal)
t6 Address hold time (referenced to the read signal)
t7 Ready signal response delay time (referenced to the read signal)
t8 Ready signal release delay time (referenced to the read signal)
t9 Read signal negate setup time (referenced to CLK)
t10 Read signal negate hold time (referenced to CLK)
t11 Data output delay time (referenced to the ready signal)
t12 Data output hold time (referenced to the read signal)
T Clock period
Minimum
10
15
10
15
0
5
12
15
60
Maximum
T + t1 + 24
t9 + 30
0
t9 + 30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
No. 4909-11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet LC8220.PDF ] | |
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