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PDF K7D323674A Data sheet ( Hoja de datos )

Número de pieza K7D323674A
Descripción 32Mb A-die DDR SRAM Specification
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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K7D323674A
K7D321874A
www.DataSheet4U.com
1Mx36 & 2Mx18 SRAM
32Mb A-die DDR SRAM Specification
153FCBGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev 1.4
Oct. 2005

1 page




K7D323674A pdf
K7D323674A
K7D321874A
www.DataSheet4U.com
1Mx36 & 2Mx18 SRAM
FUNCTIONAL BLOCK DIAGRAM
SA[0:20]( or SA[0:21])
K,K
Clock
Buffer
Advance
B1 Control
B3 SD/DD
Synchronous
Select
B2
&
R/W control
Internal
Clock
Generator
Address
Register
CE
20(or 21)
Comparator
Write
Address
Register
(2 stage)
CE
20(or 21)
18(or 19)
(Burst Address)
Burst
Counter
(Burst Write
Address)
18(or 19)
CE Strobe_out
R/W
LD Data Output Strobe
Data Output Enable
State Machine
2:1
MUX
Dec.
Data Out
Memory Array
1Mx36
or
(2Mx18)
36(or 18)x2
S/A Array
36(or 18)x2
2 : 1 MUX
Data In
36(or18)x2
W/D
Array
36(or18)x2
Write Buffer
Output
Buffer
Echo Clock
Output
Data In
Register
(2 stage)
36(or 18)
DQ
CQ,CQ
XDIN
PIN DESCRIPTION
Pin Name
K, K
SA
SA0, SA1
DQ
CQ, CQ
B1
B2
B3
LBO
ZQ
Pin Description
Differential Clocks
Synchronous Address Input
Synchronous Burst Address Input (SA0 = LSB)
Synchronous Data I/O
Differential Output Echo Clocks
Load External Address
Burst R/W Enable
Single/Double Data Selection
Linear Burst Order
Output Driver Impedance Control Input
Pin Name
TCK
TMS
TDI
TDO
VREF
VDD
VDDQ
VSS
NC
Pin Description
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
HSTL Input Reference Voltage
Power Supply
Output Power Supply
GND
No Connection
-5-
Rev 1.4
Oct. 2005

5 Page





K7D323674A arduino
K7D323674A
K7D321874A
www.DataSheet4U.com
1Mx36 & 2Mx18 SRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Core Supply Voltage Relative to VSS
VDD
-0.5 to 3.13
V
Output Supply Voltage Relative to VSS
VDDQ
-0.5 to 2.3
V
Voltage on any pin Relative to VSS
Output Short-Circuit Current(per I/O)
Storage Temperature
VIN
IOUT
TSTR
-0.5 to VDDQ+0.5 (2.3V MAX)
25
-55 to 125
V
mA
°C
Maxmum Junction Temperature
Maxmum Power Dissipation
TJ 110 °C
PD 3.0 W
NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level Voltage
Input Low Level Voltage
Input Reference Voltage
Symbol
VDD
VDDQ
VIH
VIL
VREF
Min
1.7
1.4
VREF+0.1
-0.3
0.68
Typ
2.5
1.5
-
-
0.75
Max
2.6
1.9
VDDQ+0.3
VREF-0.1
1.0
Unit
V
V
V
V
V
Note
1, 2
1, 3
NOTE :1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=2.6V (2.1V for DQs) (pulse width 20% of cycle time).
3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.0V (-0.5V for DQs) (pulse width 20% of cycle time).
DC CHARACTERISTICS
Parameter
Average Power Supply Operating Current(x36)
(Cycle time = tKHKH min)
Average Power Supply Operating Current(x18)
(Cycle time = tKHKH min)
Stop Clock Standby Current
(VIN=VDD-0.2V or 0.2V fixed, K=Low, K=High)
Input Leakage Current
(VIN=VSS or VDDQ)
Output Leakage Current
(VOUT=VSS or VDDQ)
Output High Voltage(Programmable Impedance Mode)
Output Low Voltage(Programmable Impedance Mode)
Output High Voltage(IOH=-0.1mA)
Output Low Voltage(IOL=0.1mA)
Symbol
IDD40
IDD37
IDD33
IDD40
IDD37
IDD33
ISB1
ILI
ILO
VOH1
VOL1
VOH2
VOL2
NOTE :1. Minimum cycle. IOUT=0mA.
2. 50% read cycles.
3. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175Ω ≤ RQ 300.
4. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175Ω ≤ RQ 300.
Min
-
-
-
-3
-5
VDDQ/2
VSS
VDDQ-0.2
VSS
Max
960
940
900
910
890
850
300
3
5
VDDQ
VDDQ/2
VDDQ
0.2
Unit Note
mA 1,2
mA 1,2
mA 1
µA
µA
V3
V4
V
V
- 11
Rev 1.4
Oct. 2005

11 Page







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