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PDF KFG5616U1M-DIB Data sheet ( Hoja de datos )

Número de pieza KFG5616U1M-DIB
Descripción OneNAND256 FLASH MEMORY
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! KFG5616U1M-DIB Hoja de datos, Descripción, Manual

OneNAND256
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OneNAND SPECIFICATION
Product
OneNAND256
Part No.
KFG5616Q1M-DEB
KFG5616D1M-DEB
KFG5616U1M-DIB
VCC(core & IO)
1.8V(1.7V~1.95V)
2.65V(2.4V~2.9V)
3.3V(2.7V~3.6V)
Temperature
Extended
Extended
Industrial
PKG
63FBGA(LF)/48TSOP1
63FBGA(LF)/48TSOP1
63FBGA(LF)/48TSOP1
Version: Ver. 1.2
Date: June 15th, 2005
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KFG5616U1M-DIB pdf
OneNAND256
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1. FEATURES
Architecture
Design Technology: 0.12µm
Voltage Supply
- 1.8V device(KFG5616Q1M) : 1.7V~1.95V
- 2.65V device(KFG5616D1M) : 2.4V~2.9V
- 3.3V device(KFG5616U1M) : 2.7V~3.6V
Organization
- Host Interface:16bit
Internal BufferRAM(3K Bytes)
- 1KB for BootRAM, 2KB for DataRAM
NAND Array
- Page Size : (1K+32)bytes
- Block Size : (64K+2K)bytes
Performance
Host Interface type
- Synchronous Burst Read
: Clock Frequency: up to 54MHz
: Linear Burst - 4 , 8 , 16 , 32 words with wrap-around
: Continuous Sequential Burst(512 words)
- Asynchronous Random Read
: Access time of 76ns
- Asynchronous Random Write
Programmable Read latency
Multiple Sector Read
- Read multiple sectors by Sector Count Register(up to 2 sectors)
Multiple Reset
- Cold Reset / Warm Reset / Hot Reset / NAND Flash Reset
Power dissipation (typical values, CL=30pF)
- Standby current : [email protected] device, [email protected]/3.3V device
- Synchronous Burst Read current(54MHz) : [email protected] device, [email protected]/3.3V device
- Load current : [email protected] device, [email protected]/3.3V device
- Program current: [email protected] device, [email protected]/3.3V device
- Erase current: [email protected] device, [email protected]/3.3V device
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
Hardware Features
Voltage detector generating internal reset signal from Vcc
Hardware reset input (RP)
Data Protection
- Write Protection mode for BootRAM
- Write Protection mode for NAND Flash Array
- Write protection during power-up
- Write protection during power-down
User-controlled One Time Programmable(OTP) area
Internal 2bit EDC / 1bit ECC
Internal Bootloader supports Booting Solution in system
Software Features
Handshaking Feature
- INT pin: Indicates Ready / Busy of OneNAND
- Polling method: Provides a software method of detecting the Ready / Busy status of OneNAND
Detailed chip information by ID register
Packaging
Package
- 63ball, 9.5mm x 12mm x max 1.0mmt , 0.8mm ball pitch FBGA
- 48 TSOP 1, 12mm x 20mm, 0.5mm pitch
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KFG5616U1M-DIB arduino
OneNAND256
5. BLOCK DIAGRAM
DQ15~DQ0
A15~A0
CLK
CE
OE
WE
RP
AVD
INT
RDY
BufferRAM
BootRAM
DataRAM
Bootloader
StateMachine
Internal Registers
(Address/Command/Configuration
/Status Registers)
Error
Correction
Logic
- Host Interface
- BufferRAM(BootRAM, DataRAM)
- Command and status registers
- State Machine (Bootloader is included)
- Error Correction Logic
- Memory(NAND Flash Array, OTP)
NOTE:
1) At cold reset, bootloader copies boot code(1K byte size) from NAND Flash Array to BootRAM.
Figure 1. Internal Block Diagram
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NAND Flash
Array
OTP
(One Block)
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