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PDF R4F2164 Data sheet ( Hoja de datos )

Número de pieza R4F2164
Descripción 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series
Fabricantes Renesas Technology 
Logotipo Renesas Technology Logotipo



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No Preview Available ! R4F2164 Hoja de datos, Descripción, Manual

REJ09B0429-0100
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16
H8S/2164 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2400 Series
H8S/2164 R4F2164
Rev.1.00
Revision Date: Mar. 17, 2008

1 page




R4F2164 pdf
Configuration of This Manual
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This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
CPU and System-Control Modules
On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 1.00 Mar. 17, 2008 Page v of xl

5 Page





R4F2164 arduino
5.6.4 Interrupt Response Times ....................................................................................... 93
5.6.5 DTC Activation by Interrupt................................................................................... 94
5.7 Usage Notes .............................................................................w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m.......... 96
5.7.1 Conflict between Interrupt Generation and Disabling ............................................ 96
5.7.2 Instructions that Disable Interrupts ......................................................................... 97
5.7.3 Interrupts during Execution of EEPMOV Instruction............................................. 97
5.7.4 IRQ Status Registers (ISR16, ISR) ......................................................................... 97
Section 6 Bus Controller (BSC)...........................................................................99
6.1 Features................................................................................................................................ 99
6.2 Input/Output Pins ............................................................................................................... 102
6.3 Register Descriptions ......................................................................................................... 103
6.3.1 Bus Control Register (BCR) ................................................................................. 103
6.3.2 Bus Control Register 2 (BCR2) ............................................................................ 105
6.3.3 Wait State Control Register (WSCR) ................................................................... 106
6.3.4 Wait State Control Register 2 (WSCR2) .............................................................. 108
6.3.5 System Control Register 2 (SYSCR2) .................................................................. 109
6.4 Bus Control ........................................................................................................................ 110
6.4.1 Bus Specifications................................................................................................. 110
6.4.2 Advanced Mode.................................................................................................... 117
6.4.3 I/O Select Signals.................................................................................................. 118
6.5 Bus Interface ...................................................................................................................... 119
6.5.1 Data Size and Data Alignment.............................................................................. 119
6.5.2 Valid Strobes ........................................................................................................ 121
6.5.3 Valid Strobes (in Glueless Extension) .................................................................. 122
6.5.4 Basic Operation Timing in Normal Extended Mode ............................................ 123
6.5.5 Basic Operation Timing in Address-Data Multiplex Extended Mode .................. 134
6.5.6 Wait Control ......................................................................................................... 142
6.6 Burst ROM Interface.......................................................................................................... 146
6.6.1 Basic Operation Timing........................................................................................ 146
6.6.2 Wait Control ......................................................................................................... 147
6.7 Idle Cycle........................................................................................................................... 148
6.8 Bus Arbitration................................................................................................................... 149
6.8.1 Overview............................................................................................................... 149
6.8.2 Operation .............................................................................................................. 149
6.8.3 Bus Mastership Transfer Timing .......................................................................... 150
Section 7 Data Transfer Controller (DTC) ........................................................151
7.1 Features.............................................................................................................................. 151
7.2 Register Descriptions ......................................................................................................... 153
7.2.1 DTC Mode Register A (MRA) ............................................................................. 154
7.2.2 DTC Mode Register B (MRB).............................................................................. 155
7.2.3 DTC Source Address Register (SAR)................................................................... 155
7.2.4 DTC Destination Address Register (DAR)........................................................... 155
Rev. 1.00 Mar. 17, 2008 Page xi of xl

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