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PDF R4F2125 Data sheet ( Hoja de datos )
| Número de pieza | R4F2125 | |
| Descripción | 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series | |
| Fabricantes | Renesas Technology | |
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REJ09B0310-0100
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16
H8S/2125 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2100 Series
H8S/2125
R4F2125
R4P2125
Rev.1.00
Revision Date: Sep. 21, 2006
1 page  
Configuration of This Manual
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This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
Product code, Package dimensions, etc.
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 1.00 Sep. 21, 2006 Page v of xxxviii
5 Page 
5.3.1 Interrupt Control Registers A to D (ICRA to ICRD) .......................................... 78
5.3.2
5.3.3
Address Break Control Register (ABRKCR) .........w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m.......... 79
Break Address Registers A to C (BARA to BARC)........................................... 80
5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL).................................................. 81
5.3.5 IRQ Enable Registers (IER)................................................................................ 82
5.3.6 IRQ Status Registers (ISR) ................................................................................. 82
5.4 Interrupt Sources................................................................................................................. 83
5.4.1 External Interrupt Sources .................................................................................. 83
5.4.2 Internal Interrupt Sources ................................................................................... 84
5.5 Interrupt Exception Handling Vector Tables ...................................................................... 85
5.6 Interrupt Control Modes and Interrupt Operation ............................................................... 87
5.6.1 Interrupt Control Mode 0 .................................................................................... 90
5.6.2 Interrupt Control Mode 1 .................................................................................... 92
5.6.3 Interrupt Exception Handling Sequence ............................................................. 95
5.6.4 Interrupt Response Times ................................................................................... 97
5.6.5 DTC Activation by Interrupt............................................................................... 98
5.7 Address Breaks ................................................................................................................. 100
5.7.1 Features............................................................................................................. 100
5.7.2 Block Diagram.................................................................................................. 100
5.7.3 Operation .......................................................................................................... 101
5.7.4 Usage Notes ...................................................................................................... 101
5.8 Usage Notes ...................................................................................................................... 103
5.8.1 Conflict between Interrupt Generation and Disabling ...................................... 103
5.8.2 Instructions for Disabling Interrupts ................................................................. 104
5.8.3 Interrupts during Execution of EEPMOV Instruction....................................... 104
5.8.4 External Interrupt Pin in Software Standby Mode and Watch Mode................ 104
5.8.5 Noise Canceller Switching................................................................................ 104
5.8.6 IRQ Status Register (ISR)................................................................................. 104
Section 6 Bus Controller (BSC).........................................................................105
6.1 Features............................................................................................................................. 105
6.2 Input/Output Pins.............................................................................................................. 106
6.3 Register Descriptions........................................................................................................ 107
6.3.1 Bus Control Register (BCR) ............................................................................. 107
6.3.2 Wait State Control Register (WSCR) ............................................................... 108
6.4 Bus Control....................................................................................................................... 110
6.4.1 Bus Specifications............................................................................................. 110
6.4.2 Advanced Mode................................................................................................ 111
6.4.3 Normal Mode.................................................................................................... 111
6.4.4 I/O Select Signals.............................................................................................. 112
Rev. 1.00 Sep. 21, 2006 Page xi of xxxviii
11 Page | ||
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