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PDF R4F20103 Data sheet ( Hoja de datos )
| Número de pieza | R4F20103 | |
| Descripción | 16-Bit Single-Chip Microcomputer H8S Family / H8S/Tiny Series | |
| Fabricantes | Renesas Technology | |
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REJ09B0465-0100
www.DataSheet4U.com
16
H8S/20103, H8S/20203, H8S/20223 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/Tiny Series
H8S/20103
H8S/20203
H8S/20223
R4F20103
R4F20203
R4F20223
All information contained in this material, including products and product
specifications at the time of publication of this material, is subject to change by
Renesas Technology Corp. without notice. Please review the latest information
published by Renesas Technology Corp. through various means, including the
Renesas Technology Corp. website (http://www.renesas.com).
Rev.1.00
Revision Date: Oct. 03, 2008
1 page  
How to Use This Manual
www.DataSheet4U.com
1. Objective and Target Users
This manual was written to explain the hardware functions and electrical characteristics of this
LSI to the target users, i.e. those who will be using this LSI in the design of application
systems. Target users are expected to understand the fundamentals of electrical circuits, logic
circuits, and microcomputers.
This manual is organized in the following items: an overview of the product, descriptions of
the CPU, system control functions, and peripheral functions, electrical characteristics of the
device, and usage notes.
When designing an application system that includes this LSI, take all points to note into
account. Points to note are given in their contexts and at the final part of each section, and
in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions.
It does not cover all revised items. For details on the revised points, see the actual locations
in the manual.
The following documents have been prepared for the H8S/20103 Group, H8S/20203 Group,
H8S/20223 Group. Before using any of the documents, please visit our web site to verify that
you have the most up-to-date available version of the document.
Document Type
Data Sheet
Hardware Manual
Software Manual
Application Note
Renesas Technical
Update
Contents
Document Title
Document No.
Overview of hardware and electrical
characteristics
Hardware specifications (pin
assignments, memory maps,
peripheral specifications, electrical
characteristics, and timing charts)
and descriptions of operation
H8S/20103 Group
H8S/20203 Group
H8S/20223 Group
Hardware Manual
This manual
Detailed descriptions of the CPU
and instruction set
H8S/2600 Series
H8S/2000 Series
Software Manual
REJ09B0143
Examples of applications and
sample programs
The latest versions are available from our
web site.
Preliminary report on the
specifications of a product,
document, etc.
Rev. 1.00 Oct. 03, 2008 Page v of xxvi
5 Page 
4.5 Interrupt Control Modes and Interrupt Operation ............................................................... 96
4.5.1
4.5.2
Interrupt Control Mode 0 ........................................w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m.......... 96
Interrupt Control Mode 2 .................................................................................... 98
4.5.3 Interrupt Exception Handling Sequence ........................................................... 100
4.5.4 Interrupt Response Time................................................................................... 102
4.5.5 DTC Activation by Interrupt............................................................................. 102
4.6 Usage Notes ...................................................................................................................... 103
4.6.1 Conflict between Interrupt Generation and Disabling ...................................... 103
4.6.2 Instructions that Disable Interrupts ................................................................... 104
4.6.3 Time when Interrupts are Disabled................................................................... 104
4.6.4 Interrupts during Execution of EEPMOV Instruction....................................... 104
4.6.5 Changing PMR, ISCRH, ISCRL and INCCR................................................... 105
4.6.6 IRQ Status Register (ISR)................................................................................. 105
4.6.7 NMI Pin ............................................................................................................ 106
Section 5 Clock Pulse Generator .......................................................................107
5.1 Overview........................................................................................................................... 108
5.2 Register Descriptions........................................................................................................ 110
5.2.1 Backup Control Register (BACKR) ................................................................. 111
5.2.2 System Clock Control Register (SYSCCR)...................................................... 113
5.2.3 Power-Down Control Register 1 (LPCR1) ....................................................... 115
5.2.4 Power-Down Control Register 2 (LPCR2) ....................................................... 117
5.2.5 Power-Down Control Register 3 (LPCR3) ....................................................... 118
5.2.6 OSC Oscillation Settling Control Status Register (OSCCSR).......................... 120
5.2.7 High-Speed OCO Control Register (HOCR).................................................... 121
5.2.8 High-Speed OCO Trimming Data Protect Register (HOTRMDPR) ................ 122
5.2.9 High-Speed OCO Trimming Data Register 1 (HOTRMDR1).......................... 123
5.2.10 High-Speed OCO Trimming Data Register 2 (HOTRMDR2).......................... 124
5.2.11 High-Speed OCO Trimming Data Register 3 (HOTRMDR3).......................... 124
5.2.12 High-Speed OCO Trimming Data Register 4 (HOTRMDR4).......................... 125
5.3 Operation of Selection of System Base Clock .................................................................. 126
5.3.1 Switching System Base Clock to φhoco ........................................................... 129
5.3.2 Switching System Base Clock to φosc.............................................................. 131
5.3.3 Clock Change Timing ....................................................................................... 132
5.3.4 Backup Operation ............................................................................................. 135
5.4 High-Speed On-Chip Oscillator........................................................................................ 139
5.4.1 Procedures for Switching to 32MHz................................................................. 139
5.4.2 Trimming of High-Speed OCO......................................................................... 140
5.5 Main Clock Oscillator....................................................................................................... 142
5.5.1 Connecting Crystal Resonator .......................................................................... 142
Rev. 1.00 Oct. 03, 2008 Page xi of xxvi
11 Page | ||
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