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PDF M36W0R6030B0 Data sheet ( Hoja de datos )

Número de pieza M36W0R6030B0
Descripción 64 Mbit Flash Memory and 8 Mbit SRAM Multi-Chip Package
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! M36W0R6030B0 Hoja de datos, Descripción, Manual

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M36W0R6030T0
M36W0R6030B0
64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory
and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package
FEATURES SUMMARY
MULTI-CHIP PACKAGE
– 1 die of 64 Mbit (4Mb x 16) Flash Memory
– 1 die of 8 Mbit SRAM
SUPPLY VOLTAGE
– VDDF = VDDQ = VDDS = 1.7 to 1.95V
LOW POWER CONSUMPTION
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code (Top Flash Configuration):
8810h
– Device Code (Bottom Flash
Configuration): 8811h
PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
FLASH MEMORY
PROGRAMMING TIME
– 8µs by Word typical for Fast Factory
Program
– Double/Quadruple Word Program option
– Enhanced Factory Program options
MEMORY BLOCKS
– Multiple Bank Memory Array: 4 Mbit
Banks
– Parameter Blocks (Top or Bottom
location)
SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 66MHz
– Asynchronous/ Synchronous Page Read
mode
– Random Access: 70ns
DUAL OPERATIONS
– Program Erase in one Bank while Read in
others
– No delay between Read and Write
operations
Figure 1. Package
FBGA
Stacked TFBGA88
(ZAQ)
BLOCK LOCKING
– All blocks locked at Power-up
– Any combination of blocks can be locked
– WPF for Block Lock-Down
SECURITY
– 128-bit user programmable OTP cells
– 64-bit unique device number
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
SRAM
8 Mbit (512Kb x 16 bit)
ACCESS TIME: 70ns
LOW VDDS DATA RETENTION: 1.0V
POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
December 2004
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M36W0R6030B0 pdf
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M36W0R6030T0, M36W0R6030B0
Figure 3. TFBGA Connections (Top view through package)
12345678
A DU DU
DU DU
B
A4
A18
A19
VSS
VDDF
NC
A21 A11
C
A5 LBS NC VSS E2S KF
NC A12
D
A3 A17 NC VPPF WS NC
A9 A13
E
A2
A7
NC WPF LF
A20 A10 A15
F
A1
A6
UBS
RPF
WF
A8 A14 A16
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAITF
NC
H
GS
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
NC
J
E1S
GF
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQ
K EF NC NC VDDS NC NC VDDQ NC
L
VSS
VSS
VDDQ
VDDF
VSS
VSS
VSS
VSS
M DU DU
DU DU
AI08535
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M36W0R6030B0 arduino
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M36W0R6030T0, M36W0R6030B0
SRAM OPERATIONS
There are five standard operations that control the
device. These are Read, Write, Standby/Power-
down, Data Retention and Output Disable.
Read. Read operations are used to output the
contents of the SRAM Array.
The device is in Byte Read mode whenever Write
Enable, WS, is at VIH, Output Enable, GS, is at VIL,
Chip Enable, E1S, is at VIL, Chip Enable, E2S, is at
VIH, and UBS or LBS is at VIL.
The device is in Word Read mode whenever Write
Enable, WS, is at VIH, Output Enable, GS, is at VIL,
Byte Enable inputs UBS and LBS are both at VIL
and the two Chip Enable inputs, E1S, and E2S are
Don’t Care.
The Read and Standby AC Waveforms are shown
in Figures 9 and 10, respectively and the parame-
ters are given in Table 9., Read AC Characteris-
tics.
Write. Write operations are used to write data to
the SRAM. The device is in Write mode whenever
WS, E1S and UBS and/or LBS are at VIL, and E2S
is at VIH. All these signals must be asserted to ini-
tiate a Write cycle. The data is latched on the fall-
ing edge of E1S, the rising edge of E2S, the falling
edge of WS, or the falling edge of UBS and/or LBS,
whichever occurs last. The Write cycle will termi-
nate on the rising edge of E1S, the rising edge of
WS, the rising edge of UBS and/or LBS, or the fall-
ing edge of E2S, whichever occurs first. The tim-
ings are referenced to the signal that terminates
the Write cycle.
The outputs are disabled during Write cycles
(whenever E1S, at VIL, E2S at VIH, and WS at VIL).
The Write AC Waveforms are shown in Figures
11, 12, 13 and 14, while Table 10. gives the Write
AC Characteristics.
Standby/Power-Down. The device automatically
enters the Standby/Power-Down mode when
DQ0-DQ15 are not toggling, reducing the power
consumption to the Standby level, ISB.
The device is also in Standby/Power-Down mode
whenever E1S is at VIH, E2S is at VIL or both UBS
and LBS are at VIH. The outputs then become high
impedance.
The Standby AC Waveforms are shown in Figure
10. See Table 9., Read AC Characteristics, for
timings.
Data Retention. The data retention mode is en-
tered tCDR after de-asserting E1S, E2S or UBS and
LBS. The data retention performance as VDD goes
down to VDR is described in Table 11., Figures 15
and 16, SRAM Low VDD Data Retention AC Wave-
forms, E1S or UBS / LBS Controlled and SRAM
Low VDD Data Retention AC Waveforms, E2S
Controlled, respectively.
Output Disable. The device is in the Output Dis-
able mode whenever GS, is at VIH. In this mode,
DQ0-DQ15 are high impedance.
11/26

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