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PDF RD74LVC1G240 Data sheet ( Hoja de datos )
| Número de pieza | RD74LVC1G240 | |
| Descripción | Bus Buffer Inverted | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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RD74LVC1G240
www.DataSheet4U.com
Bus Buffer Inverted with 3–state Output
Description
REJ03D0733–0100
Rev.1.00
Apr 13, 2006
The RD74LVC1G240 has bus buffer inverted with 3–state output in a 5-pin package. Low voltage and high-speed
operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption
extends the battery life.
Features
• The basic gate function is lined up as renesas uni logic series.
• Supply voltage range: 1.65 to 5.5 V
• Operating temperature range: –40 to +85°C
• All inputs: VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs: VO (Max.) = 5.5 V (@VCC = 0 V)
• Output current:
±4 mA (@VCC = 1.65 V)
±8 mA (@VCC = 2.3 V)
±24 mA (@VCC = 3.0 V)
±32 mA (@VCC = 4.5 V)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
RD74LVC1G240WPE
WCSP–5 pin SXBG0005LB–A
(TBS–5CV)
Package
Abbreviation
WP
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Article Indication
Marking
Year code
EHYM
Month code
Rev.1.00 Apr 13, 2006 page 1 of 7
1 page  
RD74LVC1G240
Switching Characteristics
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Item
Propagation delay time
Output enable time
Output disable time
Symbol
tPLH
tPHL
tZH
tZL
tHZ
tLZ
Ta = –40 to 85°C
Min Max
3.0 8.0
3.8 9.4
2.1 9.4
Unit Test Conditions
ns CL = 30 pF, RL = 1.0 kΩ
ns
ns
VCC = 1.8±0.15 V
FROM
TO
(Input) (Output)
AY
OE Y
OE Y
Item
Propagation delay time
Output enable time
Output disable time
Symbol
tPLH
tPHL
tZH
tZL
tHZ
tLZ
Ta = –40 to 85°C
Min Max
1.4 5.5
2.1 6.5
1.0 4.9
Unit Test Conditions
ns CL = 30 pF, RL = 500 Ω
ns
ns
VCC = 2.5±0.2 V
FROM
TO
(Input) (Output)
AY
OE Y
OE Y
Item
Propagation delay time
Output enable time
Output disable time
Symbol
tPLH
tPHL
tZH
tZL
tHZ
tLZ
Ta = –40 to 85°C
Min Max
1.1 4.5
1.4 5.4
1.4 5.2
Unit Test Conditions
ns CL = 50 pF, RL = 500 Ω
ns
ns
VCC = 3.3±0.3 V
FROM
TO
(Input) (Output)
AY
OE Y
OE Y
Item
Propagation delay time
Output enable time
Output disable time
Symbol
tPLH
tPHL
tZH
tZL
tHZ
tLZ
Ta = –40 to 85°C
Min Max
1.0 4.0
1.1 5.2
1.0 4.1
Unit Test Conditions
ns CL = 50 pF, RL = 500 Ω
ns
ns
VCC = 5.0±0.5 V
FROM
TO
(Input) (Output)
AY
OE Y
OE Y
Operating Characteristics
Item
Power dissipation
capacitance
Symbol
CPD
VCC (V)
1.8
2.5
3.3
5.0
Ta = 25°C
Min Typ Max
— 19 —
— 19 —
— 20 —
— 22 —
Unit Test Conditions
pF f = 10 MHz
Rev.1.00 Apr 13, 2006 page 5 of 7
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet RD74LVC1G240.PDF ] | |
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