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PDF RD74LVC16374B Data sheet ( Hoja de datos )
| Número de pieza | RD74LVC16374B | |
| Descripción | 16-bit D-type Flip Flops | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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RD74LVC16374B
www.DataSheet4U.com
16-bit D-type Flip Flops with 3-state Outputs
Description
REJ03D0501–0100
Rev.1.00
Jan. 24, 2005
The RD74LVC16374B has sixteen edge trigger D type flip flops with three state outputs in a 48 pin package. Data at
the D inputs meeting set up requirements are transferred to the Q outputs on positive going transitions of the clock
input. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high
again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless
of what signals are present at the other inputs and the state of the storage elements. Low voltage and high-speed
operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the
life of a battery for long time operation.
Features
• VCC = 1.65 V to 5.5 V
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±4 mA (@VCC = 1.65 V)
±8 mA (@VCC = 2.3 V)
±12 mA (@VCC = 2.7 V)
±24 mA (@VCC = 3.0 V to 5.5 V)
• Ordering Information
Part Name
Package Type
Package Code
Package
(Previous Code) Abbreviation
RD74LVC16374BTEL TSSOP–48 pin
PTSP0048KA–A T
(TTP–48DBV)
Taping Abbreviation
(Quantity)
EL (1,000 pcs/reel)
Function Table
Inputs
G CK D
HXX
L↑L
L ↑H
LLX
H: High level
L: Low level
X: Immaterial
Z: High impedance
↑: Low to high transition
Q0: Level of Q before the indicated steady input conditions were established.
Output Q
Z
L
H
Q0
Rev.1.00 Jan. 24, 2005 page 1 of 8
1 page  
RD74LVC16374B
Switching Characteristics
Ta = –40 to 85°C
Item
Symbol VCC (V) Min Typ Max
Maximum clock
frequency
fmax 1.8±0.15
2.5±0.2
—
—
— 55.0
— 95.0
2.7 — — 150.0
3.3±0.3
—
— 150.0
5.0±0.5
—
— 150.0
Propagation delay time
tPLH
tPHL
1.8±0.15
2.5±0.2
1.0
1.0
— 19.1
— 9.6
2.7 1.0 — 7.7
3.3±0.3
1.5
—
7.0
5.0±0.5
1.0
—
5.5
Output enable time
tZH 1.8±0.15
tZL 2.5±0.2
1.0
1.0
— 20.0
— 10.5
2.7 1.0 — 8.0
3.3±0.3
1.5
—
7.0
5.0±0.5
1.0
—
6.0
Output disable time
tHZ 1.8±0.15
tLZ 2.5±0.2
1.0
1.0
— 20.0
— 10.5
2.7 1.0 — 8.0
3.3±0.3
1.5
—
7.0
5.0±0.5
1.0
—
6.0
Setup time
tsu 1.8±0.15
2.5±0.2
6.0
4.0
—
—
—
—
2.7
2.0 —
—
3.3±0.3
2.0
—
—
5.0±0.5
2.0
—
—
Hold time
th 1.8±0.15 4.0
—
—
2.5±0.2
2.0
—
—
2.7
1.5 —
—
3.3±0.3
1.5
—
—
5.0±0.5
1.5
—
—
Pulse width
tw 1.8±0.15 9.0
—
—
2.5±0.2
4.0
—
—
2.7
3.3 —
—
3.3±0.3
3.3
—
—
5.0±0.5
3.3
—
—
Between output
pins skew*1
tOSLH
1.8±0.15
—
—
—
tOSHL
2.5±0.2
—
—
—
2.7 — — —
3.3±0.3
—
— 1.0
5.0±0.5
—
— 1.0
Input capacitance
CIN 3.3
— 4.0 —
Output capacitance CO 3.3
— 8.0 —
Note: 1. This parameter is characterized but not tested.
tosLH = | tPLHm - tPLHn|, tosHL = | tPHLm - tPHLn|
www.DataSheet4U.com
Unit
MHz
From
To
(Input) (Output)
ns CK
Q
ns G
Q
ns G
Q
ns
ns
ns
ns
pF
pF
Rev.1.00 Jan. 24, 2005 page 5 of 8
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet RD74LVC16374B.PDF ] | |
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