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PDF SCAN921226H Data sheet ( Hoja de datos )

Número de pieza SCAN921226H
Descripción High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! SCAN921226H Hoja de datos, Descripción, Manual

October 2004
www.DataSheet4U.com
SCAN921025H and SCAN921226H
High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes
with IEEE 1149.1 (JTAG) and at-speed BIST
General Description
The SCAN921025H transforms a 10-bit wide parallel
LVCMOS/LVTTL data bus into a single high speed Bus
LVDS serial data stream with embedded clock. The
SCAN921226H receives the Bus LVDS serial data stream
and transforms it back into a 10-bit wide parallel data bus
and recovers parallel clock.
Both devices are compliant with IEEE 1149.1 Standard for
Boundary Scan Test. IEEE 1149.1 features provide the de-
sign or test engineer access via a standard Test Access Port
(TAP) to the backplane or cable interconnects and the ability
to verify differential signal integrity. The pair of devices also
features an at-speed BIST mode which allows the intercon-
nects between the Serializer and Deserializer to be verified
at-speed.
The SCAN921025H transmits data over backplanes or
cable. The single differential pair data path makes PCB
design easier. In addition, the reduced cable, PCB trace
count, and connector size tremendously reduce cost. Since
one output transmits clock and data bits serially, it eliminates
clock-to-data and data-to-data skew. The powerdown pin
saves power by reducing supply current when not using
either device. Upon power up of the Serializer, you can
choose to activate synchronization mode or allow the Dese-
rializer to use the synchronization-to-random-data feature.
By using the synchronization mode, the Deserializer will
establish lock to a signal within specified lock times. In
addition, the embedded clock guarantees a transition on the
bus every 12-bit cycle. This eliminates transmission errors
due to charged cable conditions. Furthermore, you may put
the SCAN921025H output pins into TRI-STATE to achieve a
high impedance state. The PLL can lock to frequencies
between 20 MHz and 80 MHz.
Features
n High Temperature Operation to 125˚C
n IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test
mode.
n Clock recovery from PLL lock to random data patterns.
n Guaranteed transition every data transfer cycle
n Chipset (Tx + Rx) power consumption < 600 mW (typ)
@ 80 MHz
n Single differential pair eliminates multi-channel skew
n 800 Mbps serial Bus LVDS data rate (at 80 MHz clock)
n 10-bit parallel interface for 1 byte data plus 2 control bits
n Synchronization mode and LOCK indicator
n Programmable edge trigger on clock
n High impedance on receiver inputs when power is off
n Bus LVDS serial output rated for 27load
n Small 49-lead BGA package
Block Diagrams
© 2004 National Semiconductor Corporation DS201207
20120701
www.national.com

1 page




SCAN921226H pdf
Absolute Maximum Ratings (Note 1)
Supply Voltage (VCC)
LVCMOS/LVTTL Input Voltage
LVCMOS/LVTTL Output Voltage
Bus LVDS Receiver Input Voltage
−0.3V to +4V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to +3.9V
Bus LVDS Driver Output Voltage
−0.3V to +3.9V
Bus LVDS Output Short Circuit
Duration
10mS
Junction Temperature
+150˚C
Storage Temperature
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 seconds)
+220˚C
Maximum Package Power Dissipation Capacity
@ 25˚C Package:
49L BGA
1.47 W
Package Derating:
11.8 mW/˚C above
49L BGA
+25˚C
θja
ESD Rating
HBM
MM
85˚C/W
www.DataSheet4U.com
>2kV
> 250V
Recommended Operating
Conditions
Supply Voltage (VCC)
Operating Free Air
Temperature (TA)
Receiver Input Range
Supply Noise Voltage
(VCC)
Min Nom Max Units
3.0 3.3 3.6 V
−40 +25 +125 ˚C
0 2.4 V
100 mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max Units
SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN)
VIH High Level Input Voltage
2.0
VCC
V
VIL Low Level Input Voltage
GND
0.8 V
VCL Input Clamp Voltage
IIN Input Current
ICL = −18 mA
VIN = 0V or 3.6V
-0.86 −1.5
−10 ±1 +10
V
µA
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply
to pins ROUT, RCLK, LOCK = outputs)
VIH High Level Input Voltage
VIL Low Level Input Voltage
VCL Input Clamp Voltage
ICL = −18 mA
IIN Input Current
VIN = 0V or 3.6V
VOH High Level Output Voltage
IOH = −9 mA
VOL Low Level Output Voltage
IOL = 9 mA
IOS Output Short Circuit Current VOUT = 0V
IOZ TRI-STATE Output Current
PWRDN or REN = 0.8V, VOUT = 0V or VCC
SERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins DO+ and DO−)
2.0
GND
−10
2.2
GND
−15
−10
−0.62
±1
3.0
0.25
−47
±0.1
VCC
0.8
−1.5
+15
VCC
0.5
−85
+10
V
V
V
µA
V
V
mA
µA
VOD Output Differential Voltage
(DO+)–(DO−)
RL = 27, Figure 17
200 290
mV
VOD
Output Differential Voltage
Unbalance
35 mV
VOS
VOS
IOS
IOZ
IOX
Offset Voltage
Offset Voltage Unbalance
Output Short Circuit Current
TRI-STATE Output Current
Power-Off Output Current
1.05 1.1 1.3
V
4.8 35 mV
D0 = 0V, DIN = High,PWRDN and DEN =
2.4V
−56 −90 mA
PWRDN or DEN = 0.8V, DO = 0V or VCC −10 ±1 +10 µA
VCC = 0V, DO=0V or 3.6V
−20 ±1 +30 µA
5 www.national.com

5 Page





SCAN921226H arduino
AC Timing Diagrams and Test Circuits (Continued)
www.DataSheet4U.com
20120710
FIGURE 9. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays
FIGURE 10. SYNC Timing Delays
20120723
FIGURE 11. Serializer Delay
11
20120711
www.national.com

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