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PDF SCAN921224 Data sheet ( Hoja de datos )
| Número de pieza | SCAN921224 | |
| Descripción | 20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SCAN921224 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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April 2001
www.DataSheet4U.com
SCAN921023 and SCAN921224
20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer
with IEEE 1149.1 (JTAG) and at-speed BIST
General Description
The SCAN921023 transforms a 10-bit wide parallel
LVCMOS/LVTTL data bus into a single high speed Bus
LVDS serial data stream with embedded clock. The
SCAN921224 receives the Bus LVDS serial data stream and
transforms it back into a 10-bit wide parallel data bus and
recovers parallel clock. Both devices are compliant with
IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture with the incorporation of the defined
boundary-scan test logic and test access port consisting of
Test Data Input (TDI), Test Data Out (TDO), Test Mode
Select (TMS), Test Clock (TCK), and the optional Test Reset
(TRST). IEEE 1149.1 features provide the designer or test
engineer access to the backplane or cable interconnects and
the ability to verify differential signal integrity to enhance
their system test strategy. The pair of devices also features
an at-speed BIST mode which allows the interconnects be-
tween the Serializer and Deserializer to be verified at-speed.
The SCAN921023 transmits data over backplanes or cable.
The single differential pair data path makes PCB design
easier. In addition, the reduced cable, PCB trace count, and
connector size tremendously reduce cost. Since one output
transmits clock and data bits serially, it eliminates clock-to-
data and data-to-data skew. The powerdown pin saves
power by reducing supply current when not using either
device. Upon power up of the Serializer, you can choose to
activate synchronization mode or allow the Deserializer to
use the synchronization-to-random-data feature. By using
the synchronization mode, the Deserializer will establish lock
to a signal within specified lock times. In addition, the em-
bedded clock guarantees a transition on the bus every 12-bit
cycle. This eliminates transmission errors due to charged
cable conditions. Furthermore, you may put the
SCAN921023 output pins into TRI-STATE to achieve a high
impedance state. The PLL can lock to frequencies between
20 MHz and 66 MHz.
Features
n IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test
mode.
n Clock recovery from PLL lock to random data patterns.
n Guaranteed transition every data transfer cycle
n Chipset (Tx + Rx) power consumption < 500 mW (typ)
@ 66 MHz
n Single differential pair eliminates multi-channel skew
n Flow-through pinout for easy PCB layout
n 660 Mbps serial Bus LVDS data rate (at 66 MHz clock)
n 10-bit parallel interface for 1 byte data plus 2 control bits
n Synchronization mode and LOCK indicator
n Programmable edge trigger on clock
n High impedance on receiver inputs when power is off
n Bus LVDS serial output rated for 27Ω load
n Small 49-lead BGA package
Block Diagrams
© 2001 National Semiconductor Corporation DS200001
DS200001-1
www.national.com
1 page  
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
LVCMOS/LVTTL Input
Voltage
LVCMOS/LVTTL Output
Voltage
Bus LVDS Receiver Input
Voltage
−0.3V to +4V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to +3.9V
Bus LVDS Driver Output
Voltage
−0.3V to +3.9V
Bus LVDS Output Short
Circuit Duration
10mS
Junction Temperature
+150˚C
Storage Temperature
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 seconds)
+260˚C
Maximum Package Power Dissipation Capacity
@ 25˚C Package:
49L BGA
1.47 W
Package Derating:
49L BGA
θja
ESD Rating
HBM
MM
11w.8wmwW.D/˚aCtaaSbhoeveet4U.com
+25˚C
85˚C/W
>2kV
250V
Recommended Operating
Conditions
Supply Voltage (VCC)
Operating Free Air
Temperature (TA)
Receiver Input Range
Supply Noise Voltage
(VCC)
Min Nom Max Units
3.0 3.3 3.6 V
−40 +25 +85 ˚C
0 2.4 V
100 mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max Units
SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN)
VIH High Level Input Voltage
2.0
VCC
V
VIL Low Level Input Voltage
GND
0.8 V
VCL Input Clamp Voltage
ICL = −18 mA
-0.86 −1.5
V
IIN Input Current
VIN = 0V or 3.6V
−10 ±1 +10 µA
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply to
pins ROUT, RCLK, LOCK = outputs)
VIH High Level Input Voltage
VIL Low Level Input Voltage
VCL Input Clamp Voltage
ICL = −18 mA
IIN Input Current
VIN = 0V or 3.6V
IILR
Input Current, TMS, TDI,
VIN = 0V or 3.6V
TRST inputs
2.0
GND
−10
-20
−0.62
±1
-10
VCC
0.8
−1.5
+15
V
V
V
µA
µA
VOH
High Level Output Voltage
IOH = −9 mA
VOL
Low Level Output Voltage
IOL = 9 mA
IOS Output Short Circuit Current VOUT = 0V
IOS Output Short Circuit Current,
TDO output
IOZ TRI-STATE Output Current PWRDN or REN = 0.8V, VOUT = 0V or VCC
SERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins DO+ and DO−)
2.2
GND
−15
-15
3.0
0.25
−47
-70
VCC
0.5
−85
-100
−10 ±0.1 +10
V
V
mA
mA
µA
VOD Output Differential Voltage RL = 27Ω, Figure 18
(DO+)–(DO−)
200 290
mV
∆VOD
Output Differential Voltage
Unbalance
35 mV
VOS
∆VOS
IOS
IOZ
IOX
Offset Voltage
Offset Voltage Unbalance
Output Short Circuit Current
TRI-STATE Output Current
Power-Off Output Current
D0 = 0V, DIN = High,PWRDN and DEN = 2.4V
PWRDN or DEN = 0.8V, DO = 0V or VCC
VCC = 0V, DO=0V or 3.6V
1.05 1.1 1.3
V
4.8 35 mV
−56 −90 mA
−10 ±1 +10 µA
−20 ±1 +25 µA
5 www.national.com
5 Page 
AC Timing Diagrams and Test Circuits (Continued)
www.DataSheet4U.com
FIGURE 10. SYNC Timing Delays
DS200001-23
FIGURE 11. Serializer Delay
DS200001-11
FIGURE 12. Deserializer Delay
11
DS200001-12
www.national.com
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet SCAN921224.PDF ] | |
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