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PDF KK74ACT193 Data sheet ( Hoja de datos )

Número de pieza KK74ACT193
Descripción Presettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS
Fabricantes KODENSHI KOREA 
Logotipo KODENSHI KOREA Logotipo



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No Preview Available ! KK74ACT193 Hoja de datos, Descripción, Manual

TECHNICAL DATA
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KK74ACT193
Presettable 4-Bit Binary UP/DOWN Counter
High-Speed Silicon-Gate CMOS
The KK74ACT193 is identical in pinout to the LS/ALS192,
HC/HCT192. The KK74ACT193 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
The counter has two separate clock inputs, a Count Up Clock and
Count Down Clock inputs. The direction of counting is determined by
which input is clocked. The outputs change state synchronous with the
LOW-to-HIGH transitions on the clock inputs. This counter may be
preset by entering the desired data on the P0, P1, P2, P3 input. When the
Parallel Load input is taken low the data is loaded independently of either
clock input. This feature allows the counters to be used as devide-by-n by
modifying the count lenght with the preset inputs. In addition the counter
can also be cleared. This is accomplished by inputting a high on the
Master Reset input. All 4 internal stages are set to low independently of
either clock input.Both a Terminal Count Down (TCD) and Terminal
Count Up (TCU) Outputs are provided to enable cascading of both up and
down counting functions. The TCD output produces a negative going
pulse when the counter underflows and TCU outputs a pulse when the
counter overflows. The counter can be cascaded by connecting the TCU
and TCD outputs of one device to the Count Up Clock and Count Down
Clock inputs, respectively, of the next device.
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74ACT193N Plastic
KK74ACT193D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
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KK74ACT193 pdf
KK74ACT193
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TIMING REQUIREMENTS (CL=50pF, Input tr=tf=3.0 ns, VCC=5.0 V ± 10%)
Symbol
Parameter
tsu Minimum Setup Time, Pn to PL (Figure 7)
th Minimum Hold Time, PL to Pn (Figure 7)
tw Minimum Pulse Width, PL (Figure 4)
tw Minimum Pulse Width, CPU or CPD
(Figure 1)
tw Minimum Pulse Width, MR (Figure 5)
trec Minimum Recovery Time, PL to CPU or CPD (Figure
5)
trec Minimum Recovery Time, MR to CPU or CPD
(Figure 5)
Guaranteed Limits
25 °C
-40°C to
85°C
89
-1.0 -1.0
14 15
10 11
12 14
89
14 16
Unit
ns
ns
ns
ns
ns
ns
ns
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
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