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PDF LC78628E Data sheet ( Hoja de datos )

Número de pieza LC78628E
Descripción Compact Disc Player DSP with Built-in HDCD Decoder
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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No Preview Available ! LC78628E Hoja de datos, Descripción, Manual

Ordering number : ENN6329
CMOS IC
LC78628E
Compact Disc Player DSP with Built-in HDCD Decoder
®
Overview
The LC78628E CMOS IC implements signal processing
and servo control for compact disc players, laser disc
players, CD-V, CD-I, and similar products. It provides
functions for demodulation of the EFM signal from the
optical pickup, deinterleaving, error detection and
correction, and processing servo system commands issued
by the system microprocessor. In addition to this basic CD
functionality, it also provides HDCD (High Definition
Compatible Digital) decoding functions and CD text
functions. It also includes a built-in EFM PLL circuit.
Functions
• Full decoding and playback for discs encoded with the
HDCD technique developed by Pacific Microsonics,
Inc.
• Slices the high-frequency input signal at an accurate
level, converts it into the EFM signal, and generates a
PLL clock with an average frequency of 4.3218 MHz
performing a phase comparison with an internal VCO.
• Accurately generates a reference clock signal and all
necessary internal timings using an external 16.9344-
MHz crystal.
• Controls the disc motor speed using a frame phase
difference signal created based on the reproduced clock
signal and the reference clock.
• Performs detection, protection, and interpolation for the
frame synchronizing signal to assure stable data readout.
• Demodulates the EFM signal, converting it to 8-bit
symbol data.
• After applying a CRC check to the subcode Q signal,
outputs that data to the control microprocessor using
serial data transfer.
Package Dimensions
Continued on next page.
unit: mm
3174-QIP80E
0.8 0.8
64
65
[LC78628E]
23.2
20.0
0.35
1.6
41
40
0.15
80
1
25
24
2.7
21.6 0.8
SANYO: QIP80E
®
HDCD® (High Definition Compatible Digital®) is a registered trademark of Pacific Microsonics, Inc.
in the US and other countries.
A license from Pacific Microsonics, Inc. is required to use this product.
Sanyo Electric Co., Ltd. has acquired license for the use of HDCD technology from Pacific Microsonics, Inc.
The following patents apply to the design of this product:
USA: 5479168, 5638074, 5640161, 5808574, 5838274, 5854600, and 5872531.
Australia: 669114
Other patents have also been applied for.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
32400RM (OT) No. 6329-1/40

1 page




LC78628E pdf
LC78628E
Electrical Characteristics at Ta = 25°C, VDD1 = 5 V, VDD2 = 3.3 V, VSS = 0 V
Parameter
Current drain
High-level input current
Low-level input current
High-level output voltage
Low-level output voltage
Output off leakage current
Charge pump output current
Symbol
IDD1
IDD2
IIH1
IIH2
IIL
VOH1
VOH2
VOH3
VOH4
VOL1
VOL2
VOL3
VOL4
IOFF1
IPDOH
IPDOL
Conditions
min
VDD, VVDD, XVDD, LVDD, RVDD: 4.5 V to 5.5 V
VDD3V: 3.0 V to 3.6 V
DEFI, EFMIN, SCLK, COIN, RES, HFL, TES, RWC,
CQCK, TEST1, LRCKI, BCKI, DATAI, XIN: VIN = VDD1
–10
TAI, TEST2 to TEST5, CS, PCCL: VIN = VDD1
10
DEFI, EFMIN, SCLK, COIN, RES, HFL, TES, RWC,
CQCK, TAI, TEST1 to TEST5, CS, PCCL, LRCKI, BCKI,
DATAI, XIN: VIN = 0 V
–10
EFMO: IOH = –1 mA
4
CLV+, CLV, V/P, P0 to P4, PCK, FSEQ, TOFF, TGL,
JP+, JP, 16M, EMPH, LRCKO, DACKO, DFOLO,
DFORO, GAIN, MUTEL, MUTER, DOUT, EFLG, TEST6, VDD1 – 2.1
FSX, WRQ, SQOUT, TST11, DQSY, 4.2M, SRDT, LRSY,
CK2, ROMXA, C2F: IOH = –4 mA
HDCD: IOH = –12 mA
VDD1 – 2.1
LCHP, LCHN, RCHP, RCHN: IOH = –1 mA
3.0
EFMO: IOL = 1 mA
CLV+, CLV, V/P, P0 to P4, PCK, FSEQ, TOFF, TGL,
JP+, JP, 16M, EMPH, LRCKO, DACKO, DFOLO,
DFORO, GAIN, MUTEL, MUTER, DOUT, EFLG, TEST6,
FSX, WRQ, SQOUT, TST11, DQSY, 4.2M, SRDT, LRSY,
CK2, ROMXA, C2F: IOL = 4 mA
HDCD: IOL = 12 mA
LCHP, LCHN, RCHP, RCHN: IOH = 1 mA
PDO, CLV+, CLV, JP+, JP, P0 to P4, EMPH, SQOUT,
EFMO: In the high-impedance output state
0.5
–10
PDO: RISET = 68 k
PDO: RISET = 68 k
64
–96
Ratings
typ
17
55
80
–80
max
24
85
+10
Unit
mA
mA
µA
200 µA
+10 µA
V
V
V
4.5 V
1V
0.4 V
0.4 V
2.0 V
+10 µA
96 µA
–64 µA
No. 6329-5/40

5 Page





LC78628E arduino
LC78628E
Internal Functions
1. HF signal input circuit — Pin 11: EFMIN, pin 10: EFMO, pin 1: DEFI, pin 13: CLV+
HF signal
SLC
SLI
+
VREF
10 EFMO
11 EFMIN
When an HF signal is input to the EFMIN pin, an
EFM signal (NRZ) sliced at the optimal level is
acquired. As a measure to handle defects, when the
DEFI pin (pin 1) goes high, the slice level
controller output from the EFMO pin (pin 10) goes
to the high-impedance state, and the slice level is
held. However, this is only valid when the CLV
circuit is in phase control mode, that is, when the
V/P pin (pin 15) is outputting a low level.
This function can be implemented in combination
with the DEF pin from an LA9230/9240 series
A12803 product.
*: If the EFMIN and CLV+ lines are run close
together, the error rate may increase due to
spurious radiation. We recommend inserting
either a ground or VDD shield line between these
lines.
2. PLL clock regeneration circuit — Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK
VDD
Frequency
and phase
comparator
EFM(NRZ)
R1
5 ISET
Charge pump
C1
3 PDO
R2
C2
R3
7 FR
VCO
1/N
21 PCK
The LC78628E includes a built-in VCO circuit,
and a PLL circuit is formed by adding external
resistors and capacitors. The ISET pin sets the
charge pump reference current, PDO sets the VCO
circuit loop filter, and FR sets the VCO frequency
range.
Sample values for reference purposes:
R1 = 68 k, C1 = 0.1 µF
R2 = 680 , C2 = 0.1 µF
R3 = 1.2 k
A12804
Code
Command
Frequency divisor
RES = low
$AC VCO × 2 SET
$AD VCO × 1 SET
$AE VCO × 0.5 SET
1
2
0.5 q
The divisor used by the divider to create PCK from the VCO can be set using the VCO × 2, VCO × 1, and VCO × 0.5 SET instructions. Normally, the circuit
operates in the VCO × 0.5 SET state after a reset.
No. 6329-11/40

11 Page







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