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PDF IDT74ALVCH16652 Data sheet ( Hoja de datos )
| Número de pieza | IDT74ALVCH16652 | |
| Descripción | 3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT74ALVCH16652
3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER
3.3V CMOS 16-BIT BUS
TRANSCEIVER AND
REGISTER WITH 3-STATE
OUTPUTS AND BUS-HOLD
INDUSTRIALTEMPERATURERANGE
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IDT74ALVCH16652
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
This 16-bit bus transceiver and register is built using advanced dual metal
CMOS technology. The ALVCH16652 consists of D-type flip-flops and control
circuitry arranged for multiplexed transmission of data directly from the data bus
or from the internal storage registers. The device can be used as two 8-bit
transceivers or one 16-bit transceiver.
Complementary output enable (OEAB and OEBA) inputs are provided to
control the transceiver functions. Select control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. A low input
level selects real-time data, and a high input level selects stored data. Circuitry
used for select control eliminates the typical decoding glitch that occurs in a
multiplexer during the transition between stored and real-time data. Data on the
A or B bus, or both, can be stored in the internal D flip-flops by low-to-high
transition at the appropriate clock (CLKAB or CLKBA) inputs regardless of the
levels on the select control or output enable inputs. When SAB and SBA are in
the real-time transfer mode, it also is possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this
configuration, each output reinforces its input. Thus, when all other data sources
to the two sets of bus lines are in the high-impedance state, each set of bus lines
remains at its last level configuration.
The ALVCH16652 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16652 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1OEBA 56
1OEAB 1
1CLKBA 55
1SBA 54
1CLKAB 2
1SAB 3
1A1 5
A REG
D
C
B REG
D
C
2OEBA 29
2OEAB 28
2CLKBA 30
2SBA 31
2CLKAB 27
2SAB 26
52 1B1
2A1 15
A REG
D
C
B REG
D
C
42 2B1
TO 7 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
1
TO 7 OTHER CHANNELS
JANUARY 2004
DSC-4526/2
1 page  
IDT74ALVCH16652
3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER
BUS-HOLD CHARACTERISTICS
Symbol Parameter(1)
IBHH Bus-Hold Input Sustain Current VCC = 3V
IBHL
IBHH Bus-Hold Input Sustain Current VCC = 2.3V
IBHL
IBHHO
Bus-Hold Input Overdrive Current VCC = 3.6V
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
Test Conditions
VI = 2V
VI = 0.8V
VI = 1.7V
VI = 0.7V
VI = 0 to 3.6V
INDUSTRIALTEMPERATURERANGE
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Min. Typ.(2) Max. Unit
– 75 —
— µA
75 —
—
– 45 —
— µA
45 —
—
— — ±500 µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
VOH Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC = 2.3V
IOH = – 6mA
VCC = 2.3V
IOH = – 12mA
VCC = 2.7V
VCC = 3V
VCC = 3V
IOH = – 24mA
VOL OutputLOWVoltage
VCC = 2.3V to 3.6V
IOL = 0.1mA
VCC = 2.3V
IOL = 6mA
IOL = 12mA
VCC = 2.7V
IOL = 12mA
VCC = 3V
IOL = 24mA
Min. Max. Unit
VCC – 0.2
—
V
2—
1.7 —
2.2 —
2.4 —
2—
— 0.2 V
— 0.4
— 0.7
— 0.4
— 0.55
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
Symbol
CPD
CPD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
CL = 0pF, f = 10Mhz
VCC = 2.5V ± 0.2V
Typical
VCC = 3.3V ± 0.3V
Typical
Unit
pF
5
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| PDF Descargar | [ Datasheet IDT74ALVCH16652.PDF ] | |
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