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PDF ICS873991-147 Data sheet ( Hoja de datos )

Número de pieza ICS873991-147
Descripción LOW VOLTAGE LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR
ICS873991-147
GENERAL DESCRIPTION
The ICS873991-147 is a low voltage, low skew, 3.3V
ICS LVPECL or ECL Clock Generator and a member of
HiPerClockS™ the HiPerClock S ™ family of High Performance
Clock Solutions from IDT. The ICS873991-147 has
two selectable clock inputs. The PCLK, nPCLK pair
can accept an LVPECL input and the REF_CLK pin can accept
a LVCMOS or LVTTL input. This device has a fully integrated
PLL along with frequency configurable outputs. An external
feedback input and output regenerates clocks with “zero de-
lay”.
The four independent banks of outputs each have their own
output dividers, which allow the device to generate a multitude
of different bank frequency ratios and output-to-input frequency
ratios. The output frequency range is 25MHz to 500MHz and
the input frequency range is 6.25MHz to 125MHz. The PLL_SEL
input can be used to bypass the PLL for test and system debug
purposes. In bypass mode, the input clock is routed around the
PLL and into the internal output dividers.
The ICS873991-147 also has a SYNC output which can be
used for system synchronization purposes. It monitors Bank A
and Bank C outputs for coincident rising edges and signals a
pulse per the timing diagrams in this data sheet. This feature is
used primarily in applications where Bank A and Bank C are
running at different frequencies, and is particularly useful when
they are running at non-integer multiples of each other.
Example Applications:
FEATURES
Fourteen differential 3.3V LVPECL/ECL outputs
Selectable differential LVPECL or REF_CLK inputs
PCLK, nPCLK can accept the following input levels:
LVPECL, CML, SSTL
REF_CLK accepts the following input levels:
LVCMOS, LVTTL
Input clock frequency range: 6.25MHz to 125MHz
Maximum output frequency: 500MHz
VCO range: 200MHz to 1GHz
Output skew: 70ps (typical)
Cycle-to-cyle jitter: 35ps (typical)
LVPECL mode operating voltage supply range:
VCC
=
3.135V
to
3.465V,
V
EE
=
0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -3.135V
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Industrial temperature available upon request
PIN ASSIGNMENT
1. Line Card Multiplier: Multiply 19.44MHz from a back-plane
to 77.76MHz on the line card ASIC and Serdes.
2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies
from a reference clock to multiple processing units on an
embedded system.
nQB3
QB3
VCCO
nQA0
QA0
nQA1
QA1
nQA2
QA2
nQA3
QA3
SYNC_SEL
VCO_SEL
39 38 37 36 35 34 33 32 31 30 29 28 27
40 26
41 25
42 24
43 23
44 ICS873991-147 22
45 52-Lead LQFP 21
46 10mm x 10mm x 1.4mm 20
47
package body
19
48 Y package 18
49 Top View 17
50 16
51 15
52 14
1 2 3 4 5 6 7 8 9 10 11 12 13
QC1
nQC1
QC0
nQC0
VCCO
QD1
nQD1
QD0
nQD0
VCCO
QFB
nQFB
VCCA
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT/ ICSLVPECL/ECL CLOCK GENERATOR
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ICS873991AY-147 REV. A AUGUST 10, 2007

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ICS873991-147 pdf
ICS873991-147
LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
QA
QC
SYNC (QD)
QA
QC
SYNC (QD)
QA
QC
SYNC (QD)
QA
QC
SYNC (QD)
QA
QC
SYNC (QD)
1:1 Mode
2:1 Mode
3:1 Mode
3:2 Mode
4:3 Mode
FIGURE 1. TIMING DIAGRAMS
PRELIMINARY
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IDT/ ICSLVPECL/ECL CLOCK GENERATOR
5
ICS873991AY-147 REV. A AUGUST 10, 2007

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ICS873991-147 arduino
ICS873991-147
LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
www.DataSheet4U.com
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
PCLK/nPCLK INPUTS
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from PCLK to ground.
OUTPUTS:
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT
Zo = 50Ω
FIN
Zo = 50Ω
50Ω
RTT =
1
((VOH + VOL) / (VCC – 2)) – 2
Zo
50Ω
VCC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Zo = 50Ω
FIN
Zo = 50Ω
84Ω
84Ω
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
IDT/ ICSLVPECL/ECL CLOCK GENERATOR
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