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PDF R5F7142 Data sheet ( Hoja de datos )

Número de pieza R5F7142
Descripción 32-Bit RISC Microcomputer SuperH RISC engine Family
Fabricantes Renesas Technology 
Logotipo Renesas Technology Logotipo



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REJ09B0230-0300
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32
SH7147 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH™ RISC engine Family
SH7147
SH7142
R5F7147
R5F7142
Rev.3.00
Revision Date: Oct. 06, 2008

1 page




R5F7142 pdf
Preface
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The SH7147 Group RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas
Technology-original RISC CPU as its core, and the peripheral functions required to configure a
system.
Target Users: This manual was written for users who will be using the SH7147 Group in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the SH7147 Group to the target users.
Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
In order to understand the details of the CPU's functions
Read the SH-1/SH-2/SH-DSP Software Manual.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 24,
List of Registers.
Examples: Register name:
The following notation is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Rev. 3.00 Oct. 06, 2008 Page v of xxiv
REJ09B0230-0300

5 Page





R5F7142 arduino
8.2.9 DTC Vector Base Register (DTCVBR) ............................................................ 168
8.2.10 Bus Function Extending Register (BSCEHR) ........w...w..w.....D..a..t.a...S.h..e..e..t.4..U....c..o..m........ 168
8.3 Activation Sources............................................................................................................ 169
8.4 Location of Transfer Information and DTC Vector Table ................................................ 169
8.5 Operation .......................................................................................................................... 174
8.5.1 Transfer Information Read Skip Function ........................................................ 179
8.5.2 Transfer Information Write-back Skip Function............................................... 180
8.5.3 Normal Transfer Mode ..................................................................................... 180
8.5.4 Repeat Transfer Mode....................................................................................... 181
8.5.5 Block Transfer Mode ........................................................................................ 183
8.5.6 Chain Transfer .................................................................................................. 184
8.5.7 Operation Timing.............................................................................................. 186
8.5.8 Number of DTC Execution Cycles ................................................................... 187
8.5.9 DTC Bus Release Timing ................................................................................. 189
8.5.10 DTC Activation Priority Order ......................................................................... 191
8.6 DTC Activation by Interrupt............................................................................................. 192
8.7 Examples of Use of the DTC ............................................................................................ 193
8.7.1 Normal Transfer Mode ..................................................................................... 193
8.7.2 Chain Transfer when Transfer Counter = 0 ...................................................... 193
8.8 Interrupt Sources............................................................................................................... 195
8.9 Usage Notes ...................................................................................................................... 196
8.9.1 Module Standby Mode Setting ......................................................................... 196
8.9.2 On-Chip RAM .................................................................................................. 196
8.9.3 DTCE Bit Setting.............................................................................................. 196
8.9.4 Chain Transfer .................................................................................................. 196
8.9.5 Transfer Information Start Address, Source Address, and
Destination Address .......................................................................................... 196
8.9.6 Access to DTC Registers through DTC ............................................................ 196
8.9.7 Notes on IRQ Interrupt as DTC Activation Source .......................................... 197
8.9.8 Note on SCI as DTC Activation Sources.......................................................... 197
8.9.9 Clearing Interrupt Source Flag.......................................................................... 197
8.9.10 Conflict between NMI Interrupt and DTC Activation ...................................... 197
8.9.11 Operation When DTC Activation Request Is Accepted.................................... 198
Section 9 Bus State Controller (BSC)................................................................199
9.1 Features............................................................................................................................. 199
9.2 Input/Output Pins.............................................................................................................. 201
9.3 Area Overview.................................................................................................................. 202
9.3.1 Area Division .................................................................................................... 202
9.3.2 Address Map ..................................................................................................... 202
Rev. 3.00 Oct. 06, 2008 Page xi of xxiv
REJ09B0230-0300

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