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PDF K4S56323LF-FC Data sheet ( Hoja de datos )

Número de pieza K4S56323LF-FC
Descripción 2M x 32Bit x 4 Banks Mobile SDRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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K4S56323LF - F(H)E/N/S/C/L/R
Mobwilwew-.DSaDtaSRheAet4MU.com
2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
FEATURES
• VDD/VDDQ = 2.5V/2.5V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 90Balls FBGA ( -FXXX -Pb, -HXXX -Pb Free).
GENERAL DESCRIPTION
The K4S56323LF is 268,435,456 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
ORDERING INFORMATION
Part No.
K4S56323LF-F(H)E/N/S/C/L/R60
Max Freq.
166MHz(CL=3)
K4S56323LF-F(H)E/N/S/C/L/R75
K4S56323LF-F(H)E/N/S/C/L/R1H
K4S56323LF-F(H)E/N/S/C/L/R1L
133MHz(CL=3),111MHz(CL=2)
111MHz(CL=2)
111MHz(CL=3)*1
- F(H)E/N/S : Normal/Low/Super Low Power, Extended Temperature(-25°C ~ 85°C)
- F(H)C/L/R : Normal/Low/Super Low Power, Commercial Temperature(-25°C ~ 70°C)
Interface
LVCMOS
Package
90 FBGA Pb
(Pb Free)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific pur
pose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
1 May 2004

1 page




K4S56323LF-FC pdf
K4S56323LF - F(H)E/N/S/C/L/R
Mobwilwew-.DSaDtaSRheAet4MU.com
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Symbol
Test Condition
Version
Unit Note
-60 -75 -1H -1L
Operating Current
(One Bank Active)
Burst length = 1
ICC1 tRC tRC(min)
IO = 0 mA
110 100 100 90 mA 1
Precharge Standby Current ICC2P CKE VIL(max), tCC = 10ns
in power-down mode
ICC2PS CKE & CLK VIL(max), tCC =
0.5
mA
0.5
Precharge Standby Current
in non power-down mode
CKE VIH(min), CS VIH(min), tCC = 10ns
ICC2N Input signals are changed one time during
20ns
ICC2NS
CKE VIH(min), CLK VIL(max), tCC =
Input signals are stable
20
mA
8
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3P CKE VIL(max), tCC = 10ns
ICC3PS CKE & CLK VIL(max), tCC =
CKE VIH(min), CS VIH(min), tCC = 10ns
ICC3N Input signals are changed one time during
20ns
ICC3NS
CKE VIH(min), CLK VIL(max), tCC =
Input signals are stable
4
mA
2
30 mA
20 mA
Operating Current
(Burst Mode)
ICC4
IO = 0 mA
Page burst
4Banks Activated
tCCD = 2CLKs
120 100 90 90 mA 1
Refresh Current
ICC5 tRC tRC(min)
200 180 170 150
-E/C
1500
-N/L 600
Self Refresh Current
ICC6 CKE 0.2V
-S/R
Internal TCSR
Full Array
1/2 of Full Array
Max 40
450
400
Max 85/70
600
450
1/4 of Full Array
350
400
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In commercial Temp : Max 40°C/Max 70°C, In extended Temp : Max 40°C/Max 85°C
4. K4S56323LF-F(H)E/C**
5. K4S56323LF-F(H)N/L**
6. K4S56323LF-F(H)S/R**
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
mA
uA
°C
uA
2
4
5
3
6
5 May 2004

5 Page





K4S56323LF-FC arduino
K4S56323LF - F(H)E/N/S/C/L/R
Mobwilwew-.DSaDtaSRheAet4MU.com
Partial Array Self Refresh
1. In order to save power consumption, Mobile SDRAM has PASR option.
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array and 1/4 of Full Array.
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
- Full Array
- 1/2 Array
- 1/4 Array
Partial Self Refresh Area
Temperature Compensated Self Refresh
1. In order to save power consumption, Mobile-DRAM includes the internal temperature sonsor and control units to control the self
refresh cycle automatically according to the two temperature range : Max 40 °C and Max 85 °C(for Extended), Max 70 °C(for
Commercial).
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ginored.
Self Refresh Current (Icc6)
Temperature Range
- E/C
- N/L
Full Array
- S/R
1/2 of Full Array
1/4 of Full Array
Unit
Max 85/70 °C
600 450 400
1500
600
uA
Max 40 °C
450 400 350
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define PASR operating type of the device after normal MRS.
EMRS cycle is not mandatory and the EMRS command needs to be issued only when PASR is used.
The default state without EMRS command issued is all full array refreshed.
The device is now ready for the operation selected by EMRS.
For operating with PASR, set PASR mode in EMRS setting stage.
In order to adjust another mode in the state of PASR mode, additional EMRS set is required but power up sequence is not needed
again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
11 May 2004

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