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PDF MAX12559 Data sheet ( Hoja de datos )
| Número de pieza | MAX12559 | |
| Descripción | Dual 96Msps 14-Bit IF/Baseband ADC | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-3925; Rev 1; 4/07
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
Dual, 96Msps, 14-Bit, IF/Baseband ADC
General Description
The MAX12559 is a dual, 3.3V, 14-bit analog-to-digital
converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12559 is optimized for low power, small size,
and high dynamic performance in intermediate frequen-
cy (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 980mW while delivering a typical 72.2dB signal-to-
noise ratio (SNR) performance at a 175MHz input fre-
quency. The T/H input stages accept single-ended or
differential inputs up to 350MHz. In addition to low oper-
ating power, the MAX12559 features a 0.5mW power-
down mode to conserve power during idle periods.
A flexible reference structure allows the MAX12559 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the refer-
ence to be shared between the two ADCs. The refer-
ence structure allows the full-scale analog input range
to be adjusted from ±0.35V to ±1.15V. The MAX12559
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.
The MAX12559 supports either a single-ended or differ-
ential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibil-
ity and help to reduce the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC’s internal duty-cycle equalizer (DCE).
The MAX12559 features two parallel, 14-bit-wide,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two’s complement or Gray
code. A separate power-supply input for the digital out-
puts accepts a 1.7V to 3.6V voltage for flexible interfac-
ing with various logic levels. The MAX12559 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40°C to +85°C) temperature range.
For a 12-bit, pin-compatible version of this ADC, refer to
the MAX12529 data sheet. See the Selector Guide for
more selections.
Applications
IF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN
I/Q Receivers
Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
Low-Power Data Acquisition
Features
♦ Direct IF Sampling Up to 350MHz
♦ Excellent Dynamic Performance
73dB/72.2dB SNR at fIN = 70MHz/175MHz
83.5dBc/78.8dBc SFDR at fIN = 70MHz/175MHz
♦ 3.3V Low-Power Operation
980mW (Differential Clock Mode)
952mW (Single-Ended Clock Mode)
♦ Fully Differential or Single-Ended Analog Input
♦ Adjustable Differential Analog Input Voltage
♦ 750MHz Input Bandwidth
♦ Adjustable, Internal or External, Shared Reference
♦ Differential or Single-Ended Clock
♦ Accepts 25% to 75% Clock Duty Cycle
♦ User-Selectable DIV2 and DIV4 Clock Modes
♦ Power-Down Mode
♦ CMOS Outputs in Two’s Complement or Gray
Code
♦ Out-of-Range and Data-Valid Indicators
♦ Small, 68-Pin Thin QFN Package
(10mm x 10mm x 0.8mm)
♦ 12-Bit, Pin-Compatible Version Available
(MAX12529)
♦ Evaluation Kit Available (Order MAX12559EVKIT)
Ordering Information
PART
PKG
TEMP RANGE PIN-PACKAGE CODE
MAX12559ETK-D -40°C to +85°C 68 Thin QFN-EP* T6800-4
MAX12559ETK+D -40°C to +85°C 68 Thin QFN-EP* T6800-4
*EP = Exposed paddle.
+Denotes lead-free package.
D = Dry pack.
Selector Guide
PART
MAX12559
MAX12558
MAX12557
MAX12529
MAX12528
MAX12527
SAMPLING RATE
(Msps)
96
80
65
96
80
65
RESOLUTION
(Bits)
14
14
14
12
12
12
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
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Dual, 96Msps, 14-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 10pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA =
-40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
REF_P Sink Current
REF_N Source Current
COM_ Sink Current
REF_P, REF_N Capacitance
COM_ Capacitance
CLOCK INPUTS (CLKP, CLKN)
Single-Ended Input High
Threshold
Single-Ended Input Low
Threshold
Minimum Differential Clock Input
Voltage Swing
SYMBOL
CONDITIONS
IREFAP
IREFBP
VREF_P = 2.418V
IREFAN
IREFBN
VREF_N = 0.882V
ICOMA
ICOMB
VCOM_ = 1.65V
CREF_P,
CREF_N
CCOM_
VIH DIFFCLK/SECLK = GND, CLKN = GND
VIL DIFFCLK/SECLK = GND, CLKN = GND
DIFFCLK/SECLK = OVDD
MIN TYP MAX UNITS
1.2 mA
0.85 mA
0.85 mA
13 pF
6 pF
0.8 x
VDD
0.2 x
VDD
V
V
0.2 VP-P
Differential Input Common-Mode
Voltage
DIFFCLK/SECLK = OVDD
CLKP, CLKN Input Resistance
RCLK Figure 4
CLKP, CLKN Input Capacitance
CCLK
DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4, SHREF)
Input High Threshold
VIH
Input Low Threshold
VIL
Input Leakage Current
OVDD applied to input
Input connected to ground
Digital Input Capacitance
CDIN
DIGITAL OUTPUTS (D0A–D13A, D0B–D13B, DORA, DORB, DAV)
Output-Voltage Low
D0A–D13A, D0B–D13B, DORA, DORB:
VOL ISINK = 200µA
DAV: ISINK = 600µA
Output-Voltage High
VOH
D0A–D13A, D0B–D13B, DORA, DORB:
ISOURCE = 200µA
DAV: ISOURCE = 600µA
Tri-State Leakage Current
(Note 2)
ILEAK
OVDD applied to input
Input connected to ground
VDD / 2
5
2
0.8 x
OVDD
0.2 x
OVDD
±5
±5
5
V
kΩ
pF
V
V
µA
pF
OVDD -
0.2
OVDD -
0.2
0.2
V
0.2
V
±5
µA
±5
_______________________________________________________________________________________ 5
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Dual, 96Msps, 14-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL ≈ 5pF at digital outputs, VIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 96MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
SNR, SINAD vs. TEMPERATURE
(fIN = 175MHz, AIN = -1dBFS)
75
SNR
73
71
69 SINAD
67
65
63
-40
-15 10 35 60
TEMPERATURE (°C)
85
-THD, SFDR vs. TEMPERATURE
(fIN = 175MHz, AIN = -1dBFS)
90
85
SFDR
80
75
-THD
70
65
60
-40
-15 10 35 60
TEMPERATURE (°C)
85
GAIN ERROR vs. TEMPERATURE
(VREFIN = 2.048V)
3
2
1
0
-1
-2
-3
-40
-15 10 35 60
TEMPERATURE (°C)
85
OFFSET ERROR vs. TEMPERATURE
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-40
-15 10 35 60
TEMPERATURE (°C)
85
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MAX12559.PDF ] | |
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