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PDF OB2203 Datasheet ( Hoja de datos )

Número de pieza OB2203
Descripción Quasi-Resonant Flyback PWM Controller
Fabricantes On-Bright Electronics 
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OB2203 datasheet

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OB2203 pdf
OB2203
Quasi-Resonant Flyback PWM Controller
ELECTRICAL CHARACTERISTICS
(TA = 25OC, VCC=16V, if not otherwise noted)
Symbol
Parameter
Test Conditions
Min Typ Max Unit
Supply Voltage (VCC) Section
I_VCC_Startup VCC Start up Current VCC =13.5V, Measure
-
5
15 uA
current into VCC
I_VCC_quiet
Operation Current
without switching
FB=3V, CS is floating, -
2.0 3.0 mA
I_VCC_operation Operation current
with switching
FB=3V, Fsw=40KHz, 1nF -
load at GATE
3.0 4.0 mA
UVLO(ON)
VCC Under Voltage
Lockout Enter
7.5 8.5 9.5 V
UVLO(OFF)
VCC Under Voltage
Lockout Exit
(Startup)
14 15 16 V
OVP(ON)
VCC Over Voltage
Protection Enter
29 31 33 V
VCC_Clamp
VCC Zener Clamp
Voltage
I(VCC ) = 5 mA
30 32 34 V
Feedback Input Section(FB Pin)
AVCS
PWM Input Gain
VFB_Open
FB Open Voltage
ΔVFB /ΔVcs
- 3.5 - V/V
4.8 5.3 6.0 V
IFB_Short
FB pin short circuit
current
VTH_0D
Zero Duty Cycle FB
Threshold Voltage
VTH_PFM_H
PFM mode up
threshold
VTH_PFM_L
PFM mode down
threshold
VTH_BM_on
Burst Mode on
threshold
VTH_BM_off
Burst Mode off
threshold
VTH_PFC_GTS
Threshold for PFC to
go to standby
VTH_PFC_on
Threshold for PFC to
leave standby mode
VTH_PL
Power Limiting FB
Threshold Voltage
TD_PL
Power limiting
Debounce Time
ZFB_IN
Input Impedance
Current Sense Input(CS Pin) Section
T_blanking
CS Input Leading
Edge Blanking Time
VTH_OC_0
Internal current
limiting threshold
VTH_OC_60%
Internal current
limiting threshold
TD_OC
Over Current
Short FB pin to GND,
measure current
Zero duty cycle
60% duty cycle
CL=1nf at GATE,
1.0 1.5 -
mA
0.95 V
1.45 V
1.0 V
1.0 V
0.9 V
1.35 V
1.45 V
4.4 V
60 80 120 mSec
4 Kohm
350 nSec
0.43 0.45 0.47 V
0.80 V
100 160 nSec
©On-Bright Electronics
-5-
Confidential
OB_DOC_DS_0300

5 Page

OB2203 arduino
OB2203
go below 6V, which implies to unplug the SMPS
form the mains.
z OCP compensation for CCM/DCM
A proprietary OCP compensation is provided for
better OCP performance in the universal input
range. Comparing to conventional OCP
compensation where the gate delay is compensated,
more sophisticated compensation is provided to
also compensate the OCP at different line voltage
since the switching frequency varies with line
voltage. In this way, a more accurate OCP is
achieved.
z Over voltage protection (OVP)
An over voltage protection (OVP) is implemented
by sensing the auxiliary winding voltage at DEM
pin during the flyback phase. The auxiliary winding
voltage is a well-defined replica of the output
voltage. The OVP works by sampling the plateau
voltage at DEM pin during the flyback phase. A 2
us internal delay (plateau sampling) guarantees a
clean plateau, provided that the leakage inductance
ringing has been fully damped.
Quasi-Resonant Flyback PWM Controller
When over load (for example, short circuit) occurs,
the feedback current is below minimum value and a
fault is detected. If this fault is present for more
than 80ms, the controller enters an auto-recovery
soft burst mode. All pulses are stopped, VCC will
drops below UVLO and the controller will try to
restart with the power on soft start. The SMPS
enters the burst sequence and it resumes operation
once the fault disappears.
z Programmable Soft Start
OB2203 features a programmable soft start to
soften the constraints in the power supply during
the startup. It is activated during the power on
sequence. As soon as VCC reaches UVLO(OFF),
an internal trimmed 10 uA current is sourced from
SS pin and charges the external programming
capacitor, the peak current is then gradually
increased from zero. When SS pin reaches 2.2V,
soft start process is over.
UVLO(OFF)
VCC
Auxiliary
winding
R1
6
R2 DEM
OB2203
Plateau
Sampling
3.75V
Lasts for 4
subsequent cycles ?
Yes
True OVP
Figure 3
If the sampled plateau voltage exceeds the OVP trip
level (3.75V), an internal counter starts counting
subsequent OVP events. If OVP events are detected
in successive 4 cycles, the controller assumes a true
OVP and it enters a latch off mode and stops all
switching operations. The counter has been added
to prevent incorrect OVP detection which might
occur during ESD or lightning events. If the output
voltage exceeds the OVP trip level less than 4
successive cycles, the internal counter will be
cleared and no fault is asserted.
z Overload Operation
2.2V
SS
Soft start process
Time
Figure 4
During the soft start process, there is a low
frequency (40KHz) clamping to avoid the system
switching frequency going too low. Every restart
attempt is followed by soft start sequence.
z Gate Drive
The Gate pin is connected to the gate of an external
MOSFET for power switch control. Too weak the
gate drive results in higher conduction and switch
loss of MOSFET while too strong gate drive output
compromises the EMI.
Good tradeoff is achieved through the built-in
totem pole gate drive design with right output
strength and dead time control. The low idle loss
and good EMI system design is easier to achieve
with this dedicated control scheme. An internal
15V clamp is added for MOSFET gate protection at
high VCC voltage.
©On-Bright Electronics
- 11 -
Confidential
OB_DOC_DS_0300

11 Page





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