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PDF R5S72011 Data sheet ( Hoja de datos )

Número de pieza R5S72011
Descripción 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Fabricantes Renesas Technology 
Logotipo Renesas Technology Logotipo



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No Preview Available ! R5S72011 Hoja de datos, Descripción, Manual

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The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
SH7201Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperHTM RISC engine Family / SH7200 Series
R5S72011
Rev.2.00
Revision Date: Sep. 07, 2007

1 page




R5S72011 pdf
Configuration of This Manual
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This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
• Product Type, Package Dimensions, etc.
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 2.00 Sep. 07, 2007 Page v of xxviii

5 Page





R5S72011 arduino
5.2.2 Types of Reset ........................................................................................................ 97
5.2.3 Power-On Reset ..........................................................w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m.......... 98
5.2.4 Manual Reset ........................................................................................................ 100
5.3 Address Errors ................................................................................................................... 101
5.3.1 Address Error Sources .......................................................................................... 101
5.3.2 Address Error Exception Handling ....................................................................... 102
5.4 Bus Error............................................................................................................................ 102
5.4.1 Bus Error Generation Source ................................................................................ 102
5.4.2 Bus Error Exception Handling.............................................................................. 102
5.5 Register Bank Errors.......................................................................................................... 103
5.5.1 Register Bank Error Sources................................................................................. 103
5.5.2 Register Bank Error Exception Handling ............................................................. 103
5.6 Interrupts............................................................................................................................ 104
5.6.1 Interrupt Sources................................................................................................... 104
5.6.2 Interrupt Priority Level ......................................................................................... 105
5.6.3 Interrupt Exception Handling ............................................................................... 106
5.7 Exceptions Triggered by Instructions ................................................................................ 107
5.7.1 Types of Exceptions Triggered by Instructions .................................................... 107
5.7.2 Trap Instructions ................................................................................................... 108
5.7.3 Slot Illegal Instructions ......................................................................................... 108
5.7.4 General Illegal Instructions................................................................................... 108
5.7.5 Integer Division Instructions................................................................................. 109
5.7.6 Floating-point Operation Instruction .................................................................... 109
5.8 When Exception Sources Are Not Accepted ..................................................................... 110
5.9 Stack Status after Exception Handling Ends...................................................................... 111
5.10 Usage Notes ....................................................................................................................... 113
5.10.1 Value of Stack Pointer (SP) .................................................................................. 113
5.10.2 Value of Vector Base Register (VBR) .................................................................. 113
5.10.3 Address Errors Caused by Stacking of Address Error Exception Handling ......... 113
Section 6 Interrupt Controller (INTC) ...............................................................115
6.1 Features.............................................................................................................................. 115
6.2 Input/Output Pins ............................................................................................................... 117
6.3 Register Descriptions ......................................................................................................... 117
6.3.1 Interrupt Priority Registers 01, 02, 05 to 16 (IPR01, IPR02, IPR05 to IPR16) .... 119
6.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 121
6.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 122
6.3.4 Interrupt Control Register 2 (ICR2)...................................................................... 123
6.3.5 IRQ Interrupt Request Register (IRQRR)............................................................. 123
6.3.6 PINT Interrupt Enable Register (PINTER)........................................................... 125
Rev. 2.00 Sep. 07, 2007 Page xi of xxviii

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