PDF XC6VCX130T Data sheet ( Hoja de datos )

Número de pieza	XC6VCX130T
Descripción	Virtex-6 CXT Family
Fabricantes	XILINX
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No Preview Available ! 48 Virtex-6 CXT Famwiwlwy.DaDtaaShteaet4US.chomeet DS153 (v1.1) February 5, 2010 Advance Product Specification General Description Virtex®-6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb of block RAM, up to 768 DSP48E1 slices, enhanced mixed-mode clock management blocks, PCI Express® (GEN 1) compatible integrated blocks, a tri-mode Ethernet media access controller (MAC), up to 241K logic cells, and strong IP support. Using the third generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-6 CXT family also contains SelectIO™ technology with built-in digitally controlled impedance, ChipSync™ source-synchronous interface blocks, enhanced mixed-mode clock management blocks, and advanced configuration options. Customers needing higher transceiver speeds, greater I/O performance, additional Ethernet MACs, or greater capacity should instead use the Virtex-6 LXT or SXT families. Built on a 40 nm state-of-the-art copper process technology, Virtex-6 CXT FPGAs are a programmable alternative to custom ASIC technology. Virtex-6 CXT FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. Summary of Virtex-6 CXT FPGA Features • Advanced, high-performance, FPGA Logic − Real 6-input look-up table (LUT) technology − Dual LUT5 (5-input LUT) option − LUT/dual flip-flop pair for applications requiring rich register mix − Improved routing efficiency − 64-bit (or 32 x 2-bit) distributed LUT RAM option − SRL32/dual SRL16 with registered outputs option • • • Powerful mixed-mode clock managers (MMCM) − MMCM blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, input-jitter filtering, and phase-matched clock division • 36-Kb block RAM/FIFOs − Dual-port RAM blocks − Programmable - Dual-port widths up to 36 bits - Simple dual-port widths up to 72 bits − Enhanced programmable FIFO logic − Built-in optional error-correction circuitry − Optionally use each block as two independent 18 Kb blocks • • • • High-performance parallel SelectIO technology − 1.2 to 2.5V I/O operation − Source-synchronous interfacing using ChipSync™ technology − Digitally controlled impedance (DCI) active termination − Flexible fine-grained I/O banking − High-speed memory interface support with integrated write-leveling capability • • • • • • Advanced DSP48E1 slices − 25 x 18, two's complement multiplier/accumulator − Optional pipelining − New optional pre-adder to assist filtering applications − Optional bitwise logic functionality − Dedicated cascade connections Flexible configuration options − SPI and Parallel Flash interface − Multi-bitstream support with dedicated fallback reconfiguration logic − Automatic bus width detection Integrated interface blocks for PCI Express designs − Designed to the PCI Express Base Specification 1.1 − Gen1 Endpoint (2.5 Gb/s) support with GTX transceivers − x1, x2, x4, or x8 lane support per block − One virtual channel, eight traffic classes GTX transceivers: 150 Mb/s to 3.75 Gb/s Integrated 10/100/1000 Mb/s Ethernet MAC block − Supports 1000BASE-X PCS/PMA and SGMII using GTX transceivers − Supports MII, GMII, and RGMII using SelectIO technology resources 40 nm copper CMOS process technology 1.0V core voltage Two speed grades (-1 and -2) Two temperature grades (commercial and industrial) High signal-integrity flip-chip packaging available in standard or Pb-free package options Compatibility across sub-families: CXT, LXT, and SXT devices are footprint compatible in the same package © 2009–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS153 (v1.1) February 5, 2010 Advance Product Specification www.xilinx.com 1 1 page Virtex-6 CXT Family Data Sheet Table 8: Available I/O Pin/Device/Package Combinations Virtex-6 CXT Device User I/O Pins XC6VCX75T XC6VCX130T XC6VCX195T XC6VCX240T Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs Available User I/Os Differential I/O Pairs FF484 240 120 240 120 – – – – www.DataSheet4U.com Virtex-6 CXT FPGA Package FF784 FF1156 360 – 180 – 400 600 200 300 400 600 200 300 400 600 200 300 GTX Transceivers in CXT Devices CXT devices have between 8 to 16 gigabit transceiver circuits. Each GTX transceiver is a combined transmitter and receiver capable of operating at a data rate between 155 Mb/s and 3.75 Gb/s. The transmitter and receiver are independent circuits that use separate PLLs to multiply the reference frequency input by certain programmable numbers between 2 and 25, to become the bit-serial data clock. Each GTX transceiver has a large number of user-definable features and parameters. All of these can be defined during device configuration, and many can also be modified during operation DS153 (v1.1) February 5, 2010 Advance Product Specification www.xilinx.com 5 5 Page Virtex-6 CXT Family Data Sheet Virtex-6 CXT FPGA Electrical Characteristics Introduction www.DataSheet4U.com Virtex-6 CXT FPGAs are available in -2 and -1 speed grades, with -2 having the highest performance. Virtex-6 CXT FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. All specifications are subject to change without notice. Virtex-6 CXT FPGA DC Characteristics Table 9: Absolute Maximum Ratings Symbol Description Units VCCINT VCCAUX VCCO VBATT VREF VIN(3) VTS TSTG TSOL TJ Internal supply voltage relative to GND Auxiliary supply voltage relative to GND Output drivers supply voltage relative to GND Key memory battery backup supply Input reference voltage 2.5V or below I/O input voltage relative to GND(4) (user and dedicated I/Os) Voltage applied to 3-state 2.5V or below output(4) (user and dedicated I/Os) Storage temperature (ambient) Maximum soldering temperature(2) Maximum junction temperature(2) –0.5 to 1.1 –0.5 to 3.0 –0.5 to 3.0 –0.5 to 3.0 –0.5 to 3.0 –0.75 to VCCO + 0.5 –0.75 to VCCO + 0.5 –65 to 150 +220 +125 V V V V V V V °C °C °C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. For soldering guidelines and thermal considerations, see Virtex-6 FPGA Packaging and Pinout Specification. 3. 2.5V I/O absolute maximum limit applied to DC and AC signals. 4. For 2.5V I/O operation, refer to theVirtex-6 FPGA SelectIO Resources User Guide. DS153 (v1.1) February 5, 2010 Advance Product Specification www.xilinx.com 11 11 Page

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