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PDF 97SD3232 Data sheet ( Hoja de datos )

Número de pieza 97SD3232
Descripción 1 Gb SDRAM 8-Meg X 32 Bit X 4-Banks
Fabricantes Maxwell Technologies 
Logotipo Maxwell Technologies Logotipo



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No Preview Available ! 97SD3232 Hoja de datos, Descripción, Manual

97SD3232
1 Gb SDRAMwww.DataSheet4U.com
8-Meg X 32 Bit X 4-Banks
Logic Diagram (One Amplifier)
FEATURES:
• 1 Gigabit ( 8-Meg X 32-Bit X 4-Banks)
• RAD-PAK® radiation-hardened against natural space
radiation
• Total Dose Hardness:
>100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
SELTH > 85 MeV/mg/cm2 @ 25°C
• JEDEC Standard 3.3V Power Supply
• Clock Frequency: 100 MHz Operation
• Operating tremperature: -55 to +125 °C
• Auto Refresh
• Single pulsed RAS
• 2 Burst Sequence variations
Sequential (BL =1/2/4/8)
Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Power Down and Clock Suspend Modes
• LVTTL Compatible Inputs and Outputs
• Package: 132 Lead Quad Stack Pack Flat Package
DESCRIPTION:
Maxwell Technologies’ Synchronous Dynamic Random
Access Memory (SDRAM) is ideally suited for space
applications requiring high performance computing and
high density memory storage. As microprocessors
increase in speed and demand for higher density mem-
ory escalates, SDRAM has proven to be the ultimate
solution by providing bit-counts up to 1 Gigabits and
speeds up to 100 Megahertz. SDRAMs represent a sig-
nificant advantage in memory technology over traditional
DRAMs including the ability to burst data synchronously
at high rates with automatic column-address generation,
the ability to interleave between banks masking pre-
charge time
Maxwell Technologies’ patented RAD-PAK® packaging
technology incorporates radiation shielding in the micro-
circuit package. It eliminates the need for box shielding
for a lifetime in orbit or space mission. In a typical GEO
orbit, RAD-PAK® provides greater than 100 krads(Si)
radiation dose tolerance. This product is available with
screening up to Maxwell Technologies self-defined Class
K.
01.11.05 Rev 2
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
All data sheets are subject to change without notice 1
©2005 Maxwell Technologies
All rights reserved.

1 page




97SD3232 pdf
1 Gb (8-Meg X 32-Bit X 4-Banks) SDRAM
97SD3232
www.DataSheet4U.com
TABLE 5. AC Electrical Characteristics
(VCC =3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
SUBGROUPS
MIN
TYPICAL
MAX
UNIT
System clock cycle time1
(CAS latency = 2)
(CAS latency = 3)
tCK 9, 10, 11
10
7.5
ns
CLK high pulse width1,7
CLK low pulse width1,7,
Access time from CLK1,2
(CAS latency = 2)
(CAS latency = 3)
tCKH 9, 10, 11 2.5
tCKL 9, 10, 11 2.5
tAC 9, 10, 11
ns
ns
ns
6
6
Data-out hold time1,2,3
CLK to Data-out low impedance1,2,3,7
CLK to Data-out high impedance1,47,
(CAS latency = 2, 3)
tOH 9, 10, 11 2.7
tLZ
9, 10, 11
2
tHZ 9, 10, 11
ns
ns
5.4 ns
Input setup time1,5,6
CKE setup time for power down exit1
Input hold time1,6
Ref/Active to Ref/Active command period1
Active to Precharge command period1
Active command to column command 1
(same bank)
Precharge to Active command period1
Write recovery or data-in to precharge lead time1
Active( a) to Active (b) command period1
Transition time(rise and fall)7
Refresh Period
tAS, tCS,
tDS, tCES
tCESP
tAH, tCH, tDH
tCEH
tRC
tRAS
tRCD
tRP
tDPL
tRRD
tT
tREF
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
@ 105 °C
1.5
1.5
1.5
70
50
20
20
20
20
1
ns
ns
ns
120000
ns
ns
ns
ns
ns
ns
5 ns
16 6.4 ms
32 168
@ 85 °C
64
@ 70 °C
128
1. AC measurement assumes tT=1ns. Reference level for timing of input signals is 1.5V.
2. Access time is measured at 1.5V.
3. tLZ(min) definesthe time at which the outputs achieve the low impedance state.
4. tHZ(min) defines the time at which the outputs achieve the high impedance state.
5. tCES defines CKE setup time to CLK rising edge except for the power down exit command.
6. tAS/tAH: Address, tCS/tCH: /RAS, /CAS, /WE, DQM
7. Guarenteed by design (Not tested).
8. Guarenteed by Device Charactreization Testing. (Not 100% Tested)
01.11.05 Rev 2
All data sheets are subject to change without notice 5
©2005 Maxwell Technologies
All rights reserved.

5 Page





97SD3232 arduino
1 Gb (8-Meg X 32-Bit X 4-Banks) SDRAM
97SD3232
www.DataSheet4U.com
Clock suspend mode entry: The SDRAM enters clock suspend mode from active mode by setting CKE to
Low. If a command is input in the clock suspend mode entry cycle, the command is valid. The clock suspend
mode change depending on the current status (1 clock before) as described below.
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining
the bank active status.
READ suspend and READ with Auto-precharge suspend: The data being output is held ( and continues
to be output).
WRITE suspend and WRIT with Auto-precharge suspended: In this mode, external signals are not
accepted. However, the internal state is held.
Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock suspend mode exit: The SDRAM exits from clock suspend mode by setting CKE to High during the
clock suspend state.
IDLE: In this state, all banks are not selected, and have completed precharge operation.
Auto-refresh command (REF): When this command is input from the IDLE state, the SDRAM starts auto-
refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the
auto-refresh operation, refresh address and bank select address are generated inside the SDRAM. For
every auto-refresh cycle, the internal address counter is updated. Accordingly, 8192 cycles are required to
refresh the entire memory contents. Before executing the auto-refresh command, all the banks must be in
the IDLE state. In addition, since the precharge for all banks is automatically performed after auto-refresh,
no precharge command is required after auto-refresh.
Self Refresh entry (SELF)1: When this command is input during the IDLE state, the SDRAM starts self-
refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-
refresh is performed internally and automatically, external refresh operations are unnecessary.
Power down mode entry: When this command is executed during the IDLE state, the SDRAM enters
power down mode. In power down mode, power consumption is suppresses by cutting off the initial input
circuit.
Self-refresh exit: When this command is executed during self-refresh mode, the SDRAM can exit from self-
refresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state.
Power down exit: When this command is executed at power down mode, the SDRAM can exit from power
down mode. After exiting from power down mode, the SDRAM enters the IDLE state.
1. Self refresh mode should only be used at temperatures below 70°C.
01.11.05 Rev 2
All data sheets are subject to change without notice 11
©2005 Maxwell Technologies
All rights reserved.

11 Page







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