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PDF ICS843004-02 Data sheet ( Hoja de datos )
| Número de pieza | ICS843004-02 | |
| Descripción | CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS843004-02 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843004-02www.DataSheet4U.com
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS843004-02 is a 4 output LVPECL
ICS Synthesizer optimized to generate clock
HiPerClockS™ frequencies for a variety of high performance
applications and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. This device can select its input reference
clock from either a crystal input or a single-ended clock signal
and can be configured to generate a number of different output
frequencies via the 3 frequency select pins (F_SEL2:0). The
ICS843004-02 uses ICS’ 3rd generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase
jitter. This ensures that it will easily meet clocking requirements
for high-speed communication protocols such as 10 and 12
Gigabit Ethernet, 10 Gigbit Fibre Channel, and SONET. This
device is also suitable for next generation serial I/O
technologies like serial ATA and SCSI and is conveniently
packaged in a small 24-pin TSSOP package.
FUNCTION TABLE
F_SEL2
0
0
0
0
1
1
1
1
Inputs
F_SEL1 F_SEL0
00
01
10
11
00
01
10
11
M Divider
Value
18
24
24
32
32
32
32
40
N Divider
Value
3
4
8
1
2
4
8
8
BLOCK DIAGRAM
nPLL_SEL Pulldown
XTAL_IN
XTAL_OUT
OSC
TEST_CLK Pulldown
0
1
Phase
Detector
VCO
FEATURES
• Four 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Crystal input range: 14MHz - 37.78MHz
• VCO Range: 560MHz - 680MHz
• Supports the following applications:
SONET, Ethernet, Serial ATA, SCSI and HDTV
• RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.91ps (typical)
Offset
Noise Power
100Hz ............... -97.1 dBc/Hz
1kHz .............. -121.6 dBc/Hz
10kHz .............. -124.9 dBc/Hz
100kHz .............. -125.1 dBc/Hz
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
PIN ASSIGNMENT
nQ1
Q1
VCCo
Q0
1
2
3
4
24 nQ2
23 Q2
22 VCCO
21 Q3
nQ0
MR
nPLL_SEL
nc
nc
VCCA
F_SEL0
VCC
5
6
7
8
9
10
11
12
20 nQ3
19 F_SEL2
18 nXTAL_SEL
17 TEST_CLK
16 VEE
15 XTAL_IN
14 XTAL_OUT
13 F_SEL1
ICS843004-02
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
N
÷1
÷2
0 ÷3
÷4 (default)
package body
Q0 G Package
nQ0 Top View
Q1
÷8
1
nQ1
nXTAL_SEL Pulldown
MR Pulldown
F_SEL0:2
3
M
÷18
÷24
÷32 (default)
÷40
Q2
nQ2
Q3
nQ3
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843004-02www.DataSheet4U.com
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE
4C.
LVPECL
DC
CHARACTERISTICS,
V =V =V
CC CCA CCO
=
3.3V±5%, TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum
VCCO - 0.9
VCCO - 1.7
1.0
Units
V
V
V
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pf parallel resonant crystal.
Minimum Typical Maximum
Fundamental
14 37.78
50
7
Units
MHz
MHz
Ω
pF
TABLE 6.
AC
CHARACTERISTICS,
V
CC
=
V
CCA
=
V
CCO
= 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
fOUT Output Frequency
fVCO PLL VCO Lock Range
F_SEL0:F_SEL2 = 0
74.17
562.5
562.5
tsk(o) Output Skew; NOTE 1
15
tjit(Ø) RMS Phase Jitter; NOTE 2, 3
155.52MHz, 12kHz -20MHz
0.91
tL PLL Lock Time
TBD
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
450
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: Phase jitter is dependent on the input source used.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
637.5
640
580
Units
MHz
MHz
MHz
ps
ps
ms
ps
%
843004AG-02
www.icst.com/products/hiperclocks.html
5
REV. A JULY 20, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843004-02www.DataSheet4U.com
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
843004AG-02
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
Maximum
N 24
A -- 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 7.70 7.90
E 6.40 BASIC
E1 4.30 4.50
e 0.65 BASIC
L 0.45 0.75
α 0° 8°
aaa -- 0.10
Reference Document: JEDEC Publication 95, MO-153
www.icst.com/products/hiperclocks.html
11
REV. A JULY 20, 2005
11 Page | ||
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