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PDF ICS843003 Data sheet ( Hoja de datos )
| Número de pieza | ICS843003 | |
| Descripción | FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS843003 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS843003www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS843003 is a 3 differential output LVPECL
ICS Synthesizer designed to generate Ethernet refer-
HiPerClockS™ ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 31.25MHz or
26.041666MHz, 18pF parallel resonant crystal, the following fre-
quencies can be generated based on the settings of 4 frequency
select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz,
312.5MHz, 156.25MHz, and 125MHz.The 843003 has 2 output
banks, Bank A with 1 differential LVPECL output pair and Bank
B with 2 differential LVPECL output pairs.
The two banks have their own dedicated frequency select pins
and can be independently set for the frequencies mentioned
above.The ICS843003 uses ICS’3rd generation low phase noise
VCO technology and can achieve 1ps or lower typical rms phase
jitter, easily meeting Ethernet jitter requirements.The ICS843003
is packaged in a small 24-pin TSSOP package.
BLOCK DIAGRAM
OEA Pullup
DIV_SELA[1:0]
VCO_SEL Pullup
TEST_CLK Pulldown
0
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL Pullup
1
FB_DIV Pulldown
DIV_SELB[1:0]
MR Pulldown
OEB Pullup
Phase
Detector
VCO
625MHz
FB_DIV
0 = ÷20 (default)
1 = ÷24
FEATURES
• Three 3.3V LVPECL outputs on two banks, A Bank with
one LVPECL pair and B Bank with 2 LVPECL output pairs
• Using a 31.25MHz or 26.041666 crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
• VCO range: 560MHz to 700MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.51ps (typical)
• RMS phase noise at 156.25MHz
Phase noise:
Offset
Noise Power
100Hz ............... -96.8 dBc/Hz
1KHz .............. -119.1 dBc/Hz
10KHz .............. -126.4 dBc/Hz
100KHz .............. -127.0 dBc/Hz
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
PIN ASSIGNMENT
DIV_SELB0
VCO_SEL
MR
VCCO_A
QA0
nQA0
OEB
OEA
FB_DIV
VCCA
VCC
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
24 DIV_SELB1
2 3 VCCO_B
22 QB0
21 nQB0
20 QB1
19 nQB1
18 XTAL_SEL
17 TEST_CLK
16 XTAL_IN
15 XTAL_OUT
1 4 VEE
13 DIV_SELA1
ICS843003
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
0 0 ÷1
0 1 ÷2 (default)
0 1 0 ÷4
QA0 G Package
Top View
nQA0
1 1 ÷5
1
0 0 ÷1
0 1 ÷2
1 0 ÷4 (default)
1 1 ÷5
QB0
nQB0
QB1
nQB1
843003AG
www.icst.com/products/hiperclocks.html
REV. A JULY 27, 2004
1
1 page  
Integrated
Circuit
Systems, Inc.
ICS843003www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
Inputs, VI
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance, θJA
Storage Temperature, TSTG
4.6V
-0.5V to VCC + 0.5V
50mA
100mA
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
VCC
VCCA
VCCO_A, B
IEE
I
CCA
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Included in I
EE
3.135 3.3 3.465
3.135 3.3 3.465
3.135 3.3 3.465
158
15
Units
V
V
V
mA
mA
TABLE
4B.
LVCMOS
/
LVTTL
DC
CHARACTERISTICS,
V
CC
=
V
CCA
=
V
CCO_A
=
V
CCO_B
=
3.3V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions Minimum Typical Maximum
VIH Input High Voltage
DIV_SELA0:A1, FB_DIV
VIL
Input
DIV_SELB0:B1, VCO_SEL,
Low Voltage MR, OEA, OEB, XTAL_SEL
TEST_CLK
2 VCC + 0.3
-0.3 0.8
-0.3 1.3
IIH
TEST_CLK, MR, FB_DIV
Input
DIV_SELA1, DIV_SELB0
High Current DIV_SELB1, DIV_SELA0,
VCC = VIN = 3.465V
VCO_SEL, XTAL_SEL,
VCC = VIN = 3.465V
OEA, OEB
IIL
Input
Low Current
TEST_CLK, MR, FB_DIV
DIV_SELA1, DIV_SELB0
DIV_SELB1, DIV_SELA0,
VCC = 3.465V, VIN = 0V
-5
VCO_SEL, XTAL_SEL,
VCC = 3.465V, VIN = 0V
-150
OEA, OEB
150
5
Units
V
V
V
µA
µA
µA
µA
843003AG
www.icst.com/products/hiperclocks.html
5
REV. A JULY 27, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
ICS843003www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 4A and
4B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
FOUT
Zo = 50Ω
FIN
Zo = 50Ω
50Ω
RTT =
1
((VOH + VOL) / (VCC – 2)) – 2
Zo
50Ω
VCC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Zo = 50Ω
FIN
Zo = 50Ω
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
843003AG
www.icst.com/products/hiperclocks.html
11
REV. A JULY 27, 2004
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS843003.PDF ] | |
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