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PDF ICS843002I-72 Data sheet ( Hoja de datos )
| Número de pieza | ICS843002I-72 | |
| Descripción | FEMTOCLOCKS VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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FEMTOCLOCKS™ VCXO BASED WCDMA
CLOCK GENERATOR/JITTER ATTENUATOR
ICS843002I-72
GENERAL DESCRIPTION
The ICS843002I-72 is a member of the
ICS HiperClockS™ family of high performance clock
HiPerClockS™ solutions from IDT. The ICS843002I-72 is a
PLL based synchronous clock generator that is
optimized for WCDMA channel card applications
where jitter attenuation and frequency translation is needed.
The device contains two internal PLL stages that are cascaded
in series. The first PLL stage uses a VCXO which is optimized
to provide reference clock jitter attenuation and to be jitter
tolerant, and to provide a stable reference clock for the second
PLL stage. The second PLL stage provides additional frequency
multiplication (x32), and it maintains low output jitter by using a
low phase noise FemtoClock™ VCO. The device performance
and the PLL multiplication ratios are optimized to support
WCDMA applications. The VCXO requires the use of an
external, inexpensive pullable crystal. VCXO PLL uses external
passive loop filter components which are used to optimize the
PLL loop bandwidth and damping characteristics for the given
application.
FEATURES
• Two differential LVPECL outputs
• CLK input accepts the following input levels:
LVCMOS or LVTTL levels
• Output frequency: 122.88MHz (typical)
• FemtoClock VCO frequency range: 490MHz - 680MHz
• RMS phase jitter @ 122.88MHz, using a 19.2MHz crystal
(1.875MHz to 10MHz): 0.49ps (typical)
• Deterministic jitter: 30fs (typical)
• Random jitter, RMS: 2.2ps (typical)
• Full 3.3V or mixed 3.3V core/2.5V output supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
The ICS843002I-72 can accept a single-ended input. LOCK_DT
reports the lock status of VCXO PLL loop. If the reference clock
input is lost, it will set LOCK_DT to logic LOW.
Typical ICS843002I-72 configuration in WCDMA Systems:
• 19.2MHz pullable crystal
• Input Reference clock frequency: 3.84MHz
• Output clock frequency: 122.88MHz
PIN ASSIGNMENT
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
1
LF1
LF0
ISET
VCC
VCC
VEE
VEE
CLK
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
LOCK_DT
VEE
VCC
VCCO
VCCO
nQ1
Q1
VEE
ICS843002I-72
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
ICS843002BKI-72 REV. A NOVEMBER 21, 2007
1 page  
ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
www.DataSheet4U.com
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 0.9
VOL Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.5
VSWING Peak-to-Peak Output Voltage Swing
0.4
NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"Output Load Test Circuit" diagrams.
1.0
V
V
V
TABLE 5A. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
FOUT
tjit(ø)
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
122.88MHz, Integration range:
1.875MHz - 10MHz
122.88
0.49
tDJ
tRJ
tsk(o)
Deterministic Jitter; NOTE 2
Random Jitter, RMS; NOTE 2
Output Skew; NOTE 3, 4
30
2.2
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
49
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Measured using Wavecrest SIA-3000.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Maximum Units
MHz
ps
fs
ps
50 ps
550 ps
51 %
TABLE
5B.
AC
CHARACTERISTICS,
V
CC
=
3.3V±5%,
V
CCO
=
2.5V±5%,
V
EE
=
0V,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical
FOUT
tjit(ø)
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
122.88MHz, Integration range:
1.875MHz - 10MHz
122.88
0.49
tDJ
tRJ
tsk(o)
Deterministic Jitter; NOTE 2
Random Jitter, RMS; NOTE 2
Output Skew; NOTE 3, 4
30
2.2
tR
/
t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
49
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Measured using Wavecrest SIA-3000.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Maximum Units
MHz
ps
fs
ps
50 ps
550 ps
51 %
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
5
ICS843002BKI-72 REV. A NOVEMBER 21, 2007
5 Page 
ICS843002I-72
FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
www.DataSheet4U.com
LAYOUT GUIDELINE
Figure 5 shows an example of ICS843002I-72 application
schematic. In this example, the device is operated at V = 3.3V.
CC
The 19.2MHz pullable crystal is used. The bypass capacitor
should be placed as close as possible to the power pins. Two
examples of LVPECL terminations are shown in this schematic.
Additional termination approaches are shown in the LVPECL
Termination Application Note.
Logic Control Input Examples
Set Logic
VCC Input to
'1'
RU1
1K
Set Logic
VCC Input to
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
C1
SP
C2
SP
XTAL_OUT
X1
XTAL_IN
U1
2-pole loop filter for Mid Bandwidth setting
0.0001uF
C3 100K
C5
0. 1uF
VCC
R6
LF
LF
VCC
VCC
VEE
CLK
1
2
3
4
5
6
7
8
LF1
LF0
I SET
VCC
VCC
VEE
VEE
C LK
R7
8K
I C S843002I _72
VCC
LOC K_D T
R1
2.7K
LD1
LOCK_DT
VEE
VCC
VCCO
VCCO
nQ1
Q1
VEE
24
23
22
21
20
19
18
17
VCC
VC C O
VCC
VC C O
VCCO
Q1
nQ1
VCC=3.3V
VCCO=3.3V
VCC
R10 10
VCC
C6
10u
VCCA
C7
0.01u
C8
0.1u
VCCO
(U1:4)
(U1:5) (U1:22)
(U1:28)
(U1:29) (U1:30)
VCC
VC C
VC C
VCC
VCC
(U1:14)
(U1:20) (U1:21)
VCCO
VC C O
C9
0.1uF
C 10
0. 1uF
C11
0.1uF
C12
0.1uF
C 13
0. 1uF
C14
0.1uF
C15
0.1uF
C16
0.1uF
C17
0. 1uF
Q0
nQ0
3.3V
R3
133
Zo = 50 Ohm
Zo = 50 Ohm
R8
82.5
R4
133
+
-
R9
82.5
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R11 R12
50 50
Optional
Y-Termination
R13
50
FIGURE 5. SCHEMATIC OF RECOMMENDED LAYOUT
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR
11
ICS843002BKI-72 REV. A NOVEMBER 21, 2007
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ICS843002I-72.PDF ] | |
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