DataSheet.es    


PDF ICS843002I-40 Data sheet ( Hoja de datos )

Número de pieza ICS843002I-40
Descripción 175MHZ FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



Hay una vista previa y un enlace de descarga de ICS843002I-40 (archivo pdf) en la parte inferior de esta página.


Total 23 Páginas

No Preview Available ! ICS843002I-40 Hoja de datos, Descripción, Manual

175MHZ, FEMTOCLOCKTM VCXO BASED
SONET/SDH JITTER ATTENUATOR
General Description
The ICS843002I-40 is a member of the
ICS HiperClockS™ family of high performance clock
HiPerClockS™ solutions from IDT. The ICS843002I-40 is a PLL
based synchronous clock generator that is
optimized for SONET/SDH line card applications
where jitter attenuation and frequency translation is needed. The
device contains two internal PLL stages that are cascaded in
series. The first PLL stage uses a VCXO which is optimized to
provide reference clock jitter attenuation and to be jitter tolerant,
and to provide a stable reference clock for the 2nd PLL stage
(typically 19.44MHz). The second PLL stage provides additional
frequency multiplication (x32), and it maintains low output jitter by
using a low phase noise FemtoClock VCO. PLL multiplication
ratios are selected from internal lookup tables using device input
selection pins. The device performance and the PLL multiplication
ratios are optimized to support non-FEC (non-Forward Error
Correction) SONET/SDH applications with rates up to OC-48
(SONET) or STM-16 (SDH). The VCXO requires the use of an
external, inexpensive pullable crystal. VCXO PLL uses external
passive loop filter components which are used to optimize the PLL
loop bandwidth and damping characteristics for the given
line card application.
The ICS843002I-40 includes two clock input ports. Each one can
accept either a single-ended or differential input. Each input port
also includes an activity detector circuit, which reports input clock
activity through the LOR0 and LOR1 logic output pins. The two
input ports feed an input selection mux. “Hitless switching” is
accomplished through proper filter tuning. Jitter transfer and
wander characteristics are influenced by loop filter tuning, and
phase transient performance is influenced by both loop filter
tuning and alignment error between the two reference clocks.
Typical ICS843002I-40 configuration in SONET/SDH Systems:
VCXO 19.44MHz crystal
Loop bandwidth: 50Hz - 250Hz
Input Reference clock frequency selections:
19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz,
622.08MHz
Output clock frequency selections:
19.44MHz, 77.76MHz, 155.52MHz, Hi-Z
www.DataSheet4U.com
ICS843002I-40
Features
Two Differential LVPECL outputs
Selectable CLKx, nCLKx differential input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or
single-ended LVCMOS or LVTTL levels
Maximum output frequency: 175MHz
FemtoClock VCO frequency range: 560MHz - 700MHz
RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 0.81ps (typical)
Full 3.3V or mixed 3.3V core/2.5V output operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
32 31 30 29 28 27 26 25
LF1
LF0
ISET
VCC
CLK0
nCLK0
CLK_SEL
nc
1
2
3
4
5
6
7
8
24 LOR0
23 LOR1
22 nc
21 VCCO_LVCMOS
20 VCCO_LVPECL
19 nQB
18 QB
17 VEE
9 10 11 12 13 14 15 16
ICS843002I-40
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
1
ICS843002AKI-40 REV. A NOVEMBER 7, 2007

1 page




ICS843002I-40 pdf
ICS843002I-40
175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
www.DataSheet4U.com
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, VCC
Inputs, VI
Outputs, VO (LVCMOS)
Rating
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCCO_LVCMOS + 0.5V
Outputs, IO (LVPECL)
Continuos Current
Surge Current
Package Thermal Impedance, θJA
Storage Temperature, TSTG
50mA
100mA
37°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V±5%, VCCO_LVCMOS, VCCO_LVPECL = 3.3V±5% or 2.5V±5%, VEE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VCC
VCCA
Core Supply Voltage
Analog Supply Voltage
VCCO_LVCMOS,
VCCO_LVPECL
Output Supply Voltage
3.135
VCC – 0.15
3.135
2.375
3.3
3.3
3.3
2.5
3.465
VCC
3.465
2.625
V
V
V
V
IEE
ICCA
Power Supply Current
Analog Supply Current
210 mA
15 mA
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
5
ICS843002AKI-40 REV. A NOVEMBER 7, 2007

5 Page





ICS843002I-40 arduino
ICS843002I-40
175MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
www.DataSheet4U.com
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The
ICS843002I-40 provides separate power supplies to isolate any
high switching noise from the outputs to the internal PLL. VCC,
VCCA, VCCO_LVPECL and VCCO_LVCMOS should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VCC pin and also shows that VCCA requires that
an additional 10resistor along with a 10µF bypass capacitor be
connected to the VCCA pin.
3.3V
VCC
.01µF 10
VCCA
.01µF
10µF
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Single Ended Clock Input
V_REF
C1
0.1u
VCC
R1
1K
CLKx
nCLKx
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
11
ICS843002AKI-40 REV. A NOVEMBER 7, 2007

11 Page







PáginasTotal 23 Páginas
PDF Descargar[ Datasheet ICS843002I-40.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
ICS843002I-40175MHZ FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATORIntegrated Device Technology
Integrated Device Technology
ICS843002I-41700MHZ FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATORIntegrated Device Technology
Integrated Device Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar