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PDF ICS843002I Data sheet ( Hoja de datos )
| Número de pieza | ICS843002I | |
| Descripción | FEMTOCLOCKS CRYSTAL-TO-3.3V 2.5V LVPECL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS843002Iwww.DataSheet4U.com
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS843002I is a 2 output LVPECL synthesizer
ICS optimized to generate Fibre Channel reference
HiPerClockS™ clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 26.5625MHz, 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz, and
53.125MHz. The ICS843002I uses ICS’ FemtoClockTM low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS843002I is packaged in a small 20-pin
TSSOP package.
FEATURES
• Two 3.3V or 2.5V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @212.5MHz (2.55MHz - 20MHz):
0.50ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
FREQUENCY SELECT FUNCTION TABLE
Input
Frequency
26.5625
F_SEL1
0
Inputs
F_SEL0
M Divider
Value
0 24
N Divider
Value
3
M/N
Divider Value
8
Output
Frequency
(MHz)
212.5
26.5625
0
1
24
4
6 159.375
26.5625
1
0
24
6
4 106.25
26.5625
1
1
24
12
2 53.125
23.4375
0
0
24
3
8 187.5
BLOCK DIAGRAM
F_SEL[1:0] Pulldown
nPLL_SEL Pulldown
REF_CLK Pulldown
26.5625MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL Pulldown
1
0
2
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
1
0
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
PIN ASSIGNMENT
nc 1
2 0 VCCO
VCCO 2
19 Q1
Q0 3 18 nQ1
nQ0 4
17 VEE
MR 5
16 VCC
nPLL_SEL 6 15 nXTAL_SEL
nc 7 14 REF_CLK
VCCA 8
13 XTAL_IN
F_SEL0 9 12 XTAL_OUT
VCC 10 11 F_SEL1
ICS843002I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
Q0
nQ0
Q1
nQ1
M = 24 (fixed)
MR Pulldown
843002AGI
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 4, 2006
1 page  
Integrated
Circuit
Systems, Inc.
ICS843002Iwww.DataSheet4U.com
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
186.67
fOUT Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
140
93.33
F_SEL[1:0] =11
46.67
tsk(o) Output Skew; NOTE 1, 2
212.5MHz, (2.55MHz - 20MHz)
0.50
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
159.375MHz, (1.875MHz - 20MHz)
106.25MHz, (637kHz - 5MHz)
0.55
0.75
53.125MHz, (637kHz - 5MHz)
0.76
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0] ≠ 00
F_SEL[1:0] = 00
350
49
43
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measured using crystal input.
Maximum
226.67
170
113.33
56.67
30
650
51
57
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
%
%
843002AGI
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 4, 2006
5 Page 
Integrated
Circuit
Systems, Inc.
ICS843002Iwww.DataSheet4U.com
FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V
LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
Figure 5A shows a schematic example of the ICS843002I. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an
18pF parallel resonant 26.5625MHz crystal is used. The
C1=27pF and C2=33pF are recommended for frequency ac-
curacy. For different board layout, the C1 and C2 may be
slightly adjusted for optimizing frequency accuracy.
VCC
R2
10 C3
10uF
Logic Control Input Examples
VC C A
C4
0.01u
VCC
C6
0.1u
Set Logic
VCC Input to
'1'
RU1
1K
To Logic
Input
pins
RD1
Not Install
Set Logic
VCC Input to
'0'
RU2
Not Install
To Logic
Input
pins
RD2
1K
ICS843002I
C2
33pF
X1
26.5625MHz
18pF
C1
27pF
VCCO
C7
0.1u
U1
ICS843002i
VCC=3.3V
VCCO=3.3V
VCCO
C8
0.1u
3.3V
R3
133
Zo = 50 Ohm
Zo = 50 Ohm
R4
82.5
R5
133
+
-
R6
82.5
Zo = 50 Ohm
Zo = 50 Ohm
R7
50
+
-
R8
50
C9
0.1u
R9
50
Optional Termination
FIGURE 5A. ICS843002I SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 5B shows an example of ICS843002I P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age.The footprints of other components in this example are listed
in the Table 6. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3 0805
C4, C5, C6, C7, C8
0603
R2 0603
NOTE: Table 6, lists component sizes
shown in this layout example.
FIGURE 5B. ICS843002I PC BOARD LAYOUT EXAMPLE
843002AGI
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11
REV. A JANUARY 4, 2006
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS843002I.PDF ] | |
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