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Número de pieza ICS843002-31
Descripción 700MHZ FEMTOCLOCKS VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
Fabricantes Integrated Circuit Systems 
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843002-31www.DataSheet4U.com
700MHZ FEMTOCLOCKS™VCXO BASED
FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
GENERAL DESCRIPTION
The ICS843002-31 is a member of the
ICS HiperClockS™ family of high performance clock
HiPerClockS™ solutions from ICS. This monolithic device is a
high-performance, PLL-based synchronous
clock generator and jitter attenuation circuit. The
ICS843002-31 contains two clock multiplication stages that
are cascaded in series. The first stage is a VCXO-based PLL
that is optimized to provide reference clock jitter attenuation,
to be jitter tolerant, and to provide a stable reference clock
for the second multiplication stage. The second stage is the
proprietary ICS FemtoClock™circuit which is a high-frequency,
sub-picosecond clock multiplier.
The VCXO PLL has an on-chip VCXO circuit that uses an
external, inexpensive pullable crystal in the 17.5 to 25MHz
range. The PLL includes 13 bit reference and feedback
dividers supporting complex PLL multiplication ratios and
input reference clock rates as low as 2.3kHz. External loop
filter components are used (two resistors and two capacitors)
to achieve the low loop bandwidth needed for jitter atten-
uation of a recovered data clock.
The FemtoClock circuit can multiply the VCXO crystal
frequency by a factor of 28 or 32 (selectable) and provide a
clock output of up to 700MHz.
Clock Input/Output Configuration:
• Clock Inputs - one differential pair, two singled ended
(mux selected)
• Differential input pair can support LVPECL, LVDS,
LVHSTL, SSTL, HCSL or single-ended LVCMOS
or LVTTL levels
• Singled ended inputs can support LVCMOS or
LVTTL levels
• Clock Outputs, FemtoClockS two LVPECL pairs
(selectable output dividers)
• Clock Output, VCXO – one single ended output
(at VCXO crystal frequency)
• Clock Output, other – VCXO reference clock
Example Applications:
• SONET/SDH line card clock generator (up to 622.08MHz
for OC-48) using 8kHz frame clock as input reference
• Jitter attenuation of a recovered communications clock
• Complex-ratio clock frequency translation between
various communication protocols, such as:
• For telecom, OC-12 to E3 rate conversion, 622.08MHz
to 34.368MHz, PLL ratio of 179/32
• For digital video, ITU-R601 to SMPTE 252M/59.94,
27MHz to 74.17582MHz, PLL ratio of 250/91
FEATURES
Outputs:
Two high frequency differential LVPECL outputs
Output frequency: up to 700MHz
One LVCMOS/LVTTL VCXO PLL output with output
enable
One Reference clock output with output enable
One LOCK detect output
Input mux supports 3 selectable inputs: one differential
input pair and two LVCMOS/LVTTL input clocks
13-bit VCXO PLL feedback and reference dividers provide
wide range of frequency translation ratio options
FemtoClock frequency multiplier supports rate of:
560MHz - 700MHz
‘Lock Detect’ output reports lock status of VCXO PLL
VCXO PLL circuit provides jitter attenuation with
loop bandwidth of 250Hz and below (user adjustable)
RMS phase jitter, random at 12kHz to 20MHz:
<1ps (design target)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
LF1
LF0
ISET
VEE
NV1
NV0
VCC
MR
CLK0
nCLK0
OE_REF
CLK1
VCC
SEL1
SEL0
CLK2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
6 ICS843002-31 43
7 64-Lead TQFP, EPAD
8 10mm x 10mm x 1.0mm
9
10
package body
11 Y package
12 Top View
42
41
40
39
38
37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VEE
REF_CLK
VCLK
LOCK
VCCO_CMOS
nQB
QB
VEE
nQA
QA
VCCO_PECL
MP
NPB0
NPB1
NPB2
VCCA
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
1

1 page




ICS843002-31 pdf
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843002-31www.DataSheet4U.com
700MHZ FEMTOCLOCKS™VCXO BASED
FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS (CONTINUED FROM PREVIOUS PAGE)
Number
Name
Type
Description
49, 50,
51, 52,
53, 54,
55, 56,
57, 58,
59. 60
61
62, 63
XOFB12:XOFB1
XOFB0
XTAL_OUT,
XTAL_IN
Input
Pulldown
VCXO feedback divider control input.
LVCMOS/LVTTL interface levels.
Input
Input
Pullup
VCXO feedback divider control input.
LVCMOS/LVTTL interface levels.
VCXO crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
64
VCCA_XO
Power
Analog power supply pin for VCXO.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
(per LVCMOS output)
RPULLUP
RPULLDOWN
R
OUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
V V V VCC, CCA, CCA_XO, CCO_CMOS,
VCCO_PECL = 3.465V
Minimum Typical Maximum Units
4 pF
TBD
pF
51 kΩ
51 kΩ
7Ω
843002CY-31
www.icst.com/products/hiperclocks.html
5
REV. B NOVEMBER 22, 2005

5 Page





ICS843002-31 arduino
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843002-31www.DataSheet4U.com
700MHZ FEMTOCLOCKS™VCXO BASED
FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
843002CY-31
www.icst.com/products/hiperclocks.html
11
REV. B NOVEMBER 22, 2005

11 Page







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