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PDF ICS843002-01 Data sheet ( Hoja de datos )

Número de pieza ICS843002-01
Descripción FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Fabricantes Integrated Circuit Systems 
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No Preview Available ! ICS843002-01 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICS843002-01www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS843002-01 is a 2 output LVPECL
ICS synthesizer optimized to generate Ethernet
HiPerClockS™ reference clock frequencies and is a member of
the HiPerClocksTM family of high performance
clock solutions from ICS. Using a 25MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins
(F_SEL[1:0]): 156.25MHz, 125MHz, and 62.5MHz. The
ICS843002-01 uses ICS’ 3rd generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase
jitter, easily meeting Ethernet jitter requirements. The
ICS843002-01 is packaged in a small 20-pin TSSOP package.
FEATURES
• Two 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following input frequencies:
156.25MHz, 125MHz and 62.5MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz-20MHz): 0.54ps (typical)
• Typical phase noise at 156.25MHz
Phase noise:
Offset
Noise Power
100Hz ............... -97.3 dBc/Hz
1KHz .............. -119.1 dBc/Hz
10KHz .............. -126.4 dBc/Hz
100KHz .............. -127.6 dBc/Hz
• Full 3.3V supply mode
• Lead-Free package fully RoHS compliant
FREQUENCY SELECT FUNCTION TABLE
Inputs
F_SEL1
F_SEL0
M Divider
Value
N Divider
Value
0 0 25
4
0 1 25
5
10
25
10
11
Not Used
• -30°C to 85°C ambient operating temperature
Output Frequency
(25MHz Ref.)
156.25
125
62.5
Not Used
PIN ASSIGNMENT
nc 1
2 0 VCCO
VCCO 2
19 Q1
Q0 3 18 nQ1
nQ0 4
17 VEE
MR 5
16 VCC
nPLL_SEL 6 15 nXTAL_SEL
nc 7 14 TEST_CLK
VCCA 8
13 XTAL_IN
F_SEL0 9 12 XTAL_OUT
VCC 10 11 F_SEL1
BLOCK DIAGRAM
F_SEL[1:0] Pulldown
nPLL_SEL Pulldown
2
TEST_CLK Pulldown
25MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL Pulldown
1
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
1
0
F_SEL[1:0]
0 0 ÷4
0 1 ÷5
1 0 ÷10
1 1 not used
ICS843002-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
Q0 G Package
nQO Top View
Q1
nQ1
M = 25 (fixed)
MR Pulldown
843002AG-01
www.icst.com/products/hiperclocks.html
1
REV. B MAY 6, 2005

1 page




ICS843002-01 pdf
843002AG-01
Integrated
Circuit
Systems, Inc.
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ICS843002-01www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 62.5MHZ
10 Gigabit Ethernet Filter
62.5MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.79ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
1k
10k 100k 1M
10M 100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 125MHZ
10 Gigabit Ethernet Filter
125MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.60ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
1k
10k 100k 1M
10M 100M
OFFSET FREQUENCY (HZ)
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
5

5 Page





ICS843002-01 arduino
Integrated
Circuit
Systems, Inc.
ICS843002-01www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core) = V * I = 3.63V * 135mA = 490mW
MAX
CC_MAX EE_MAX
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.63V, with all outputs switching) = 490mW + 60mW = 550mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.550W * 66.6°C/W = 121.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
114.5°C/W
73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843002AG-01
www.icst.com/products/hiperclocks.html
11
REV. B MAY 6, 2005

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