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PDF ICS843002 Data sheet ( Hoja de datos )
| Número de pieza | ICS843002 | |
| Descripción | FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS843002www.DataSheet4U.com
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS843002 is a 2 output LVPECL synthesizer
ICS optimized to generate Fibre Channel reference
HiPerClockS™ clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 26.5625MHz, 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz, and
53.125MHz. The ICS843002 uses ICS’ 3rd generation low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS843002 is packaged in a small 20-pin
TSSOP package.
FEATURES
• Two 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter (637kHz - 10MHz): 0.72ps (typical)
• Typical phase noise at 212.5MHz
Phase noise:
Offset
Noise Power
100Hz ............... -87.7 dBc/Hz
1KHz .............. -111.6 dBc/Hz
10KHz .............. -124.3 dBc/Hz
100KHz .............. -124.3 dBc/Hz
• Full 3.3V supply mode
• Lead-Free package RoHS compliant
• -30°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
Input
Frequency
(MHz)
26.5625
F_SEL1
Inputs
F_SEL0
M Divider
Value
N Divider
Value
M/N
Divider Value
Output
Frequency
(MHz)
0 0 24
3
8 212.5
26.5625
0
1
24
4
6 159.375
26.5625
1
0
24
6
4 106.25
26.5625
1
1
24
12
2 53.125
23.4375
0
0
24
3
8 187.5
BLOCK DIAGRAM
F_SEL[1:0] Pulldown
nPLL_SEL Pulldown
TEST_CLK Pulldown
26.5625MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL Pulldown
1
0
2
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
1
0
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
PIN ASSIGNMENT
nc 1
20 VCCO
VCCO 2
19 Q1
Q0 3 18 nQ1
nQ0 4
17 VEE
MR 5
16 VCC
nPLL_SEL 6 15 nXTAL_SEL
nc 7 14 TEST_CLK
VCCA 8
13 XTAL_IN
F_SEL0 9 12 XTAL_OUT
VCC 10 11 F_SEL1
ICS843002
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
Q0
nQ0
Q1
nQ1
MR Pulldown
843002AG
M = 24 (fixed)
www.icst.com/products/hiperclocks.html
1
REV. B MAY 6, 2005
1 page  
843002AG
Integrated
Circuit
Systems, Inc.
ICS843002www.DataSheet4U.com
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
TYPICAL PHASE NOISE AT 53.125MHZ
53.125MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.97ps (typical)
Fibre Channel Jitter Filter
Raw Phase Noise Data
Phase Noise Result by adding
Fibre Channel Filter to raw data
100 1k 10k 100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
TYPICAL PHASE NOISE AT 106.25MHZ
106.25MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.84ps (typical)
Fibre Channel Jitter Filter
Raw Phase Noise Data
Phase Noise Result by adding
Fibre Channel Filter to raw data
100 1k 10k 100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
5
5 Page 
Integrated
Circuit
Systems, Inc.
ICS843002www.DataSheet4U.com
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 135mA = 490mW
• Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power (3.63V, with all outputs switching) = 490mW + 60mW = 550mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.550W * 66.6°C/W = 121.6°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
114.5°C/W
73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
843002AG
www.icst.com/products/hiperclocks.html
11
REV. B MAY 6, 2005
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS843002.PDF ] | |
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