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PDF ICS843001-21 Data sheet ( Hoja de datos )
| Número de pieza | ICS843001-21 | |
| Descripción | FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS843001-21www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS843001-21 is a a highly versatile, low
ICS phase noise LVPECL Synthesizer which can
HiPerClockS™ generate low jitter reference clocks for a variety
of communications applications and is a
member of the HiPerClocksTM family of high
performance clock solutions from ICS. The dual
crystal interface allows the synthesizer to support up to
two communications standards in a given application (i.e.
1GB Ethernet with a 25MHz crystal and 1Gb Fibre Channel
using a 25.5625MHz crystal). The rms phase jitter
performance is typically less than 1ps, thus making the
device acceptable for use in demanding applications such
as OC48 SONET and 10Gb Ethernet. The ICS843001-21
is packaged in a small 24-pin TSSOP package.
FEATURES
• One 3.3V LVPECL output pair and one LVCMOS output
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• VCO range: 560MHz - 700MHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.80ps (typical)
Offset
Noise Power
100Hz ............... -60.3 dBc/Hz
1kHz ............... -88.5 dBc/Hz
10kHz ............. -111.9 dBc/Hz
100kHz ............. -113.0 dBc/Hz
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
N2:N0
3
SEL0 Pulldown
SEL1 Pulldown
XTAL_IN0
XTAL_OUT0
OSC
XTAL_IN1
XTAL_OUT1
OSC
TEST_CLK Pulldown
00
01
10
MR Pulldown
M2:M0
3
OE_REF Pulldown
843001AG-21
11
Phase
Detector
VCO
10
01
00
M
000 ÷18
001 ÷22
010 ÷24
011 ÷25
100 ÷32 (default)
101 ÷40
N
000 ÷1
001 ÷2
010 ÷3
011 ÷4 (default)
100 ÷5
101 ÷6
110 ÷8
111 ÷10
PIN ASSIGNMENT
VCCO_CMOS
N0
N1
N2
VCCO_PECL
Q0
nQ0
VEE
VCCA
VCC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
24 REF_CLK
23 VEE
22 REF_OE
21 M2
20 M1
19 M0
18 MR
17 SEL1
16 SEL0
15 TEST_CLK
14 XTAL_IN0
13 XTAL_OUT0
ICS843001-21
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
Q0
nQ0
www.icst.com/products/hiperclocks.html
1
REF_CLK
REV. A OCTOBER 26, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS843001-21www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_PECL - 2V.
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum
VCCO - 0.9
VCCO - 1.7
1.0
Units
V
V
V
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum Units
Fundamental
MHz
12 40 MHz
50 Ω
7 pF
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
fOUT
tPD
tjit(Ø)
fVCO
tR / tF
Output Frequency
Propagation Delay, TEST_CLK to
NOTE 1
REF_CLK
RMS Phase Jitter, (Random);
NOTE 2, 3
PLL VCO Lock Range
Output
Rise/Fall Time
LVPECL
LVCMOS
622.08MHz (12kHz - 20MHz)
20% to 80%
20% to 80%
56
2.3
560
200
300
LVPECL
odc Output Duty Cycle
LVCMOS
NOTE 1: Measured from the VCC/2 of the input to VCCO_CMOS/2 of the output.
NOTE 2: Phase jitter measured using a 19.44MHz quartz crystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
45
44
Typical
0.80
Maximum Units
700 MHz
2.8 ns
ps
700 MHz
500 ps
800 ps
55 %
56 %
843001AG-21
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 26, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
ICS843001-21www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
• For logic high, V = V = V – 0.9V
OUT
OH_MAX
CC_MAX
(V - V ) = 0.9V
CCO_MAX OH_MAX
• For logic low, V = V = V – 1.7V
OUT
OL_MAX
CC_MAX
(V - V ) = 1.7V
CCO_MAX OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V – (V - 2V))/R ] * (V - V ) = [(2V - (V
- V ))/R ] * (V - V ) =
OH_MAX
CC_MAX
L CC_MAX OH_MAX
CC_MAX
OH_MAX
L
CC_MAX OH_MAX
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V – (V - 2V))/R ] * (V - V ) = [(2V - (V
- V ))/R ] * (V - V ) =
OL_MAX
CC_MAX
L CC_MAX OL_MAX
CC_MAX
OL_MAX
L
CC_MAX OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843001AG-21
www.icst.com/products/hiperclocks.html
11
REV. A OCTOBER 26, 2005
11 Page | ||
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