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PDF ICS8430002 Data sheet ( Hoja de datos )

Número de pieza ICS8430002
Descripción High-Performance Fractional-N Frequency Synthesizer
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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High-Performance Fractional-N
Frequency Synthesizer
ICS8430002
www.DataSheet4U.com
DATA SHEET
General Description
The ICS8430002 is a general purpose, high-
ICS performance, fractional-n LVPECL frequency
HiPerClockS™ synthesizer which can generate frequencies for a wide
variety of applications with output frequency step sizes
of <10ppm. The ICS8430002 has a 2:1 input
Multiplexer from which either a crystal input or a differential input can
be selected. The differential input can be wired to accept
single-ended signals (see the applications section of this datasheet).
Each of the differential LVPECL outputs has an output divider which
can be independently set so that two different frequencies can be
generated. Additionally, each LVPECL output pair has a dedicated
power supply pin so the outputs can run at 3.3V or 2.5V. The
ICS8430002 also supplies a buffered copy of the reference clock or
crystal frequency on the single-ended REF_OUT pin which can be
enabled or disabled (disabled by default). The output frequency can
be programmed using either a serial or parallel programming
interface.
The device features a fractional feedback divider with a 6-bit integer
and 12-bit fractional value. The minimum step value of the feedback
divider is 1/4096.
Features
6-Bit Integer and 12-Bit Fractional Feedback Divider
Dual differential 3.3V LVPECL outputs which can be set
independently for either 3.3V or 2.5V
2:1 Input Mux:
One differential input
One crystal oscillator interface
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
Output frequency range: 30.625MHz to 640MHz
Crystal input frequency range: 12MHz to 40MHz
VCO range: 490MHz to 650MHz
Parallel or serial interface for programming feedback divider and
output dividers
Supply voltage modes:
Core/Outputs:
3.3V/3.3V
3.3V/2.5V
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
P2
NB0
NB1
NB2
OE_REF
OEA
OEB
VCC
NA0
NA1
NA2
VEE
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 ICS8430002 34
4 48 Lead LQFP 33
5 7mm x 7mm x 1.4mm 32
6
7
package body
31
30
8 Y Package 29
9 Top View
10
28
27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
nc
nc
XTAL_OUT
XTAL_IN
nc
nc
SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
ICS8430002AY REVISION C NOVEMBER 12, 2009
1
©2009 Integrated Device Technology, Inc.

1 page




ICS8430002 pdf
ICS8430002 Data Sheet
The internal registers T0 and T1 determine the state of the TEST
output as follows:
T1 T0 TEST Output
0 0 LOW
0 1 S_DATA, Shift Register Output
1 0 Reserved
1 1 Reserved
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
www.DataSheet4U.com
The function of the DS1, and DS0 bits is as follows:
DS1 DS0 Function
0 0 Integer Mode Only
1 1 Fractional Mode Only
0 1 Do Not Use
1 0 Do Not Use
Table 1. Pin Descriptions
Number
1, 47, 48
2, 3
4
5
Name
P2, P0, P1
NB0, NB1
NB2
OE_REF
6 OEA
7
8, 14
9, 10
11
12, 24
13
15, 16
17
18, 19
20
21
22
23, 31, 32,
35, 36
OEB
VCC
NA0, NA1
NA2
VEE
TEST
FOUTA,
nFOUTA
VCCO_A
FOUTB,
nFOUTB
VCCO_B
REF_OUT
VCCO_REF
nc
25 MR
26 S_CLOCK
continued on next page.
Type
Input Pulldown
Input
Pullup
Input Pulldown
Input Pulldown
Input
Pullup
Input
Pullup
Power
Input
Input
Power
Output
Pullup
Pulldown
Description
Pre-divider control input pins. See table 3C. LVCMOS/LVTTL interface levels.
Determines output divider value as defined in Table 3D, Function Table.
LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of REF_OUT output. When HIGH,
the output is active. When LOW, the output is high-impedance. LVCMOS/LVTTL
interface levels.
Output enable. Controls enabling and disabling of FOUTA, nFOUTA outputs.
When HIGH, the outputs are active. When LOW, the true output is low and the
compliment output is high. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTB, nFOUTB outputs.
When HIGH, the outputs are active. When LOW, the true output is low and the
compliment output is high. LVCMOS/LVTTL interface levels.
Core supply pins.
Determines output divider value as defined in Table 3D, Function Table.
LVCMOS/LVTTL interface levels.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Output
Differential output pair for the synthesizer. LVPECL interface levels.
Power
Output supply pin for FOUTA/nFOUTA LVPECL outputs.
Output
Differential output pair for the synthesizer. LVPECL interface levels.
Power
Output
Power
Output supply pin for FOUTB/nFOUTB LVPECL outputs.
Reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REF_OUT.
Unused
No internal connection.
Input
Input
Pulldown
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs FOUTx to go low and the inverted outputs nFOUTx to go
high. When Logic LOW, the internal dividers and the outputs are enabled.
Assertion of MR does not affect loaded M, N, and T values.
LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register on the rising
edge of S_CLOCK. LVCMOS/LVTTL interface levels.
ICS8430002AY REVISION C NOVEMBER 12, 2009
5
©2009 Integrated Device Technology, Inc.

5 Page





ICS8430002 arduino
ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Table 5. Input Frequency Characteristics, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
XTAL_IN, XTAL_OUT; NOTE 1
fIN
Input
Frequency
PCLK/nPCLK; NOTE 2
S_CLOCK
tR / tF
Rise/Fall
Time
S_CLOCK, S_DATA, S_LOAD
www.DataSheet4U.
Minimum
12
9
Typical
Maximum
40
800
40
Units
MHz
MHz
MHz
6 ns
M = MINT + MCALC. The M value must be set for the VCO range to operate within the 490MHz - 650MHz range.
When MFRAC = 0, set bits DS1=0 and DS0 = 0
NOTE 1: Using the minimum crystal input frequency of 12MHz, valid values of M are 40.8333 M 54.1667. This means that MINT has a
range of 40 MINT 54 assuming the MFRAC is used to meet the requirement 40.8333 M 54.1667. When used, adjust MFRAC to adjust the
value of M according to the instructions on page 3. Using the maximum crystal input frequency of 40MHz, valid values of M are 12.25 M
16.25. This means that MINT has a range of 12 MINT 16.25 assuming the MFRAC is used to meet the requirement 12.25 M 16.25. When
used, adjust MFRAC to adjust the value of M according to the instructions on page 3.
NOTE 2: Using the PCLK/nPCLK input frequency of 9MHz, when the pre-divider = 1, valid values of M are 54.4444 MINT 58. This means
that MINT has a range of 54 MINT 58 assuming the MFRAC is used to meet the requirement 54.4444 M 58. MINT must not be set higher
than 58. Using the PCLK/nPCLK input frequency of 50MHz, when the pre-divider = 1, valid values of M are 10 M 13. This means that MINT
has a range of 10 MINT 13 assuming the MFRAC is used to meet the requirement 10 M 13. MINT must not be set lower than 10.
Table 6. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum Typical Maximum
Fundamental
12 40
50
7
Units
MHz
pF
ICS8430002AY REVISION C NOVEMBER 12, 2009
11
©2009 Integrated Device Technology, Inc.

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