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PDF ICS843023 Data sheet ( Hoja de datos )
| Número de pieza | ICS843023 | |
| Descripción | 3.3V 250MHZ LVPECL CLOCK GENERATOR | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS843023 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843023www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-
3.3V, 250MHZ LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
ICS
The ICS843023 is a Gigabit Ethernet Clock
Generator and a member of the HiPerClocksTM
HiPerClockS™ family of high performance devices from ICS. The
ICS843023 uses a 25MHz crystal to synthesize
250MHz.The ICS843023 has excellent phase jitter
performance, over the 1.875MHz – 20MHz integration range.
The ICS843023 is packaged in a small 8-pin TSSOP, making it
ideal for use in systems with limited board space.
FEATURES
• 1 differential 3.3V LVPECL output
• Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
• Maximum output frequency: 250MHz, using a 25MHz crystal
• VCO range: 490MHz - 640MHz
• RMS phase jitter @ 250MHz, using a 25MHz crystal
(12KHz - 20MHz): 0.33ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
OE
XTAL_IN
XTAL_OUT
25MHz
OSC
Phase
Detector
VCO
÷20
(fixed)
÷2
(fixed)
PIN ASSIGNMENT
VCC 1
8 Q0
XTAL_OUT 2
7 nQ0
XTAL_IN 3
6 VCC
Q0
VEE 4
5 OE
nQ0
ICS843023
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843023AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843023www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-
3.3V, 250MHZ LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
The ICS843023 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 1 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
X1
18pF Parallel Crystal
XTAL_OUT
C1
33p
XTAL_IN
C2
27p
Figure 1. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT
Zo = 50Ω
FIN
Zo = 50Ω
50Ω
RTT =
1
(VOH + VOL / VCC – 2) – 2
Zo
50Ω
VCC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Zo = 50Ω
FIN
Zo = 50Ω
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
843023AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 30, 2004
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ICS843023.PDF ] | |
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