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PDF TC74HC74AP Data sheet ( Hoja de datos )
| Número de pieza | TC74HC74AP | |
| Descripción | CMOS Digital Integrated Circuit Silicon Monolithic Dual D-Type Flip Flop Preset and Clear | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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TC74HC74AP/AF/AFN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic www.DataSheet4U.com
TC74HC74AP,TC74HC74AF,TC74HC74AFN
Dual D-Type Flip Flop Preset and Clear
The TC74HC74A is a high speed CMOS D FLIP FLOP
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
The signal level applied to the D INPUT is transferred to Q
OUTPUT during the positive going transition of the CLOCK
pulse.
CLEAR and PRESET are independent of the CLOCK and
are accomplished by setting the appropriate input to an “L” level.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: fmax = 77 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 2 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2~6 V
• Pin and function compatible with 74LS74
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HC74AP
TC74HC74AF
TC74HC74AFN
Weight
DIP14-P-300-2.54
SOP14-P-300-1.27A
SOL14-P-150-1.27
: 0.96 g (typ.)
: 0.18 g (typ.)
: 0.12 g (typ.)
1 2007-10-01
1 page  
Timing Requirements (input: tr = tf = 6 ns)
Characteristics
Symbol
Minimum pulse width
(CK)
Minimum pulse width
( CLR , PR )
tW (L)
tW (H)
tW (L)
Minimum set-up time
ts
Minimum hold time
Minimum removal time
( CLR , PR )
Clock frequency
th
trem
f
Test Condition
⎯
⎯
⎯
⎯
⎯
⎯
TC74HC74AP/AF/AFN
www.DataSheet4U.com
VCC (V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta = 25°C
Typ. Limit
⎯ 75
⎯ 15
⎯ 13
⎯ 75
⎯ 15
⎯ 13
⎯ 75
⎯ 15
⎯ 13
⎯0
⎯0
⎯0
⎯ 25
⎯5
⎯4
⎯6
⎯ 31
⎯ 36
Ta =
−40
~85°C
Limit
95
19
16
95
19
16
95
19
16
0
0
0
30
6
5
5
25
29
Unit
ns
ns
ns
ns
ns
MHz
AC Characteristics (CL = 15 pF, VCC = 5 V, Ta = 25°C, input: tr = tf = 6 ns)
Characteristics
Symbol
Test Condition
Min Typ. Max Unit
Output transition time
Propagation delay time
(CK-Q, Q )
Propagation delay time
( CLR , PR -Q, Q )
Maximum clock frequency
tTLH
tTHL
tpLH
tpHL
tpLH
tpHL
fmax
⎯ ⎯ 6 12 ns
⎯ ⎯ 13 26 ns
⎯ ⎯ 14 26 ns
⎯ 36 77 ⎯ MHz
5 2007-10-01
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet TC74HC74AP.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TC74HC74AF | CMOS Digital Integrated Circuit Silicon Monolithic Dual D-Type Flip Flop Preset and Clear | Toshiba Semiconductor |
| TC74HC74AFN | CMOS Digital Integrated Circuit Silicon Monolithic Dual D-Type Flip Flop Preset and Clear | Toshiba Semiconductor |
| TC74HC74AP | CMOS Digital Integrated Circuit Silicon Monolithic Dual D-Type Flip Flop Preset and Clear | Toshiba Semiconductor |
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