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PDF IDT71T016SA Data sheet ( Hoja de datos )
| Número de pieza | IDT71T016SA | |
| Descripción | 2.5V CMOS Static RAM 1 Meg (64K x 16-Bit) | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
www.DataSheet4U.com
IDT71T016SA
Features
x 64K x 16 advanced high-speed CMOS Static RAM
x Equal access and cycle times
— Commercial: 10/12/15/20ns
— Industrial: 12/15/20ns
x One Chip Select plus one Output Enable pin
x Bidirectional data inputs and outputs directly
LVTTL-compatible
x Low power consumption via chip deselect
x Upper and Lower Byte Enable Pins
x Single 2.5V power supply
x Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball
Plastic FBGA packages
Functional Block Diagram
Description
The IDT71T016 is a 1,048,576-bit high-speed Static RAM organized
as 64K x 16. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71T016 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71T016 are LVTTL-compatible and operation is from a
single 2.5V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71T016 is packaged in a JEDEC standard a 44-pin Plastic
SOJ, 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
Output
OE Enable
Buffer
A0 – A15
Address
Buffers
Chip
CS Enable
Buffer
Write
WE Enable
Buffer
BHE
BLE
Byte
Enable
Buffers
©2004 Integrated Device Technology, Inc.
Row / Column
Decoders
64K x 16
Memory
Array
8
Sense
16 Amps
and
Write
Drivers
8
High
Byte
I/O
Buffer
Low
Byte
I/O
Buffer
I/O15
8
I/O8
I/O7
8
I/O0
5326 drw 01
APRIL 2004
1
DSC-5326/01
1 page  
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
www.DataSheet4U.com
AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71T016SA10(2)
71T016SA12
71T016SA15
71T016SA20
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time
10 ____ 12 ____ 15 ____ 20 ____ ns
tAA Address Access Time
____ 10 ____ 12 ____ 15 ____ 20 ns
tACS Chip Select Access Time
____ 10 ____ 12 ____ 15 ____ 20 ns
tCLZ(1)
Chip Select Low to Output in Low-Z
4 ____ 4 ____ 5 ____ 5 ____ ns
tCHZ(1)
Chip Select Hig h to Output in High-Z
____
5 6____ ____
6 ____ 8 ns
tOE Output Enable Low to Output Valid ____ 5 6____ ____ 7 ____ 8 ns
tOLZ(1)
Output Enable Lo w to Output in Low-Z
0
____
0 ____
0
____
0 ____ ns
tOHZ(1)
Output Enable High to Output in High-Z
____
5 6____ ____
6 ____ 8 ns
tOH Output Hold from Address Change
4 — 4 — 4 — 4 — ns
tBE Byte Enable Low to Output Valid
— 5 — 6 — 7 ____ 8 ns
tBLZ(1)
Byte Enable Low to Output in Low-Z
0 ____ 0 ____ 0 ____ 0 ____ ns
tBHZ(1)
Byte Enable Hig h to Output in High-Z
____
5 6____ ____
6 ____ 8 ns
WRITE CYCLE
tWC Write Cycle Time
10 ____ 12 ____ 15 ____ 20 ____ ns
tAW Address Valid to End of Write
7 ____ 8 ____ 10 ____ 12 ____ ns
tCW Chip Select Low to End of Write
7 ____ 8 ____ 10 ____ 12 ____ ns
tBW Byte Enable Low to End of Write
7 ____ 8 ____ 10 ____ 12 ____ ns
tAS Address Set-up Time
0 ____ 0 ____ 0 ____ 0 ____ ns
tWR Address Ho ld from End of Write
0 ____ 0 ____ 0 ____ 0 ____ ns
tWP Write Pulse Width
7 ____ 8 ____ 10 ____ 12 ____ ns
tDW Data Valid to End of Write
5 ____ 6 ____ 7 ____ 9 ____ ns
tDH Data Hold Time
0 ____ 0 ____ 0 ____ 0 ____ ns
tOW(1) Write Enable Hig h to Output in Low-Z 3 ____ 3 ____ 3 ____ 3 ____ ns
tWHZ(1)
Write Enable Lo w to Output in High-Z
____
5 6____ ____
6 ____ 8 ns
NOTES:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. 00C to +700C temperature range only.
5326 tbl 10
Timing Waveform of Read Cycle No. 1(1,2,3)
ADDRESS
DATAOUT
tRC
tOH
PREVIOUS DATAOUT VALID
tAA
tOH
DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
6.452
5326 drw 06
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IDT71T016SA.PDF ] | |
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