PDF ICSSSTV32852 Data sheet ( Hoja de datos )

Número de pieza	ICSSSTV32852
Descripción	DDR 24-Bit to 48-Bit Registered Buffer
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. ICSSSTV32852 www.DataSheet4U.com DDR 24-Bit to 48-Bit Registered Buffer Recommended Application: • DDR Memory Modules • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signals • Supports SSTL_2 class II specifications on inputs and outputs • Low-voltage operation - VDD = 2.3V to 2.7V • Available in 114 ball BGA package. Truth Table1 Inputs Q Outputs Pin Configuration 123456 A B C D E F G H J K L M RESET# L H H H CLK X or Floating ↑ ↑ L or H CLK# X or Floating ↓ ↓ L or H D X or Floating H L X Q L H L Q0(2) N P R T U V W Notes: 114-Pin Ball BGA 1. H = "High" Signal Level L = "Low" Signal Level ↑ = Transition "Low"-to-"High" ↓ = Transition "High"-to-"Low" X = Don't Care 2. Output level before the indicated steady state input conditions were established. Block Diagram CLK CLK# RESET# D1 VREF R CLK D1 To 23 Other Channels Pin Configuration Assignments 1 A Q2A B Q3A C Q5A D Q7A E Q8A F Q10A G Q12A H Q13A J Q14A K Q17A L Q18A Q1A M Q20A N Q22A Q1B P Q23A R Q24A T D2 U D4 V D5 W D8 2 Q1A VDDQ Q4A Q6A GND Q9A Q11A VDD Q15A Q16A Q19A VDDQ Q21A VDDQ VDD D1 D3 D7 D9 3 CLK GND VDDQ GND VDDQ VDDQ GND VDDQ GND VDDQ GND GND VDDQ GND RESET# D6 D10 D11 D12 4 CLK# GND VDDQ GND VDDQ VDDQ GND VDDQ GND VDDQ GND GND VDDQ GND VREF D18 D22 D23 D24 5 Q1B VDDQ Q4B Q6B GND Q9B Q11B VDD Q15B Q16B Q19B VDDQ Q21B VDDQ VDD D13 D15 D19 D21 6 Q2B Q3B Q5B Q7B Q8B Q10B Q12B Q13B Q14B Q17B Q18B Q20B Q22B Q23B Q24B D14 D16 D17 D20 0513F—05/13/03 1 page ICSSSTV32852 www.DataSheet4U.com Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL PARAMETERS VDD = 2.5V ±0.2V MIN MAX fclock tPD tRST tSL tS Clock frequency Clock to output time Reset to output time Output slew rate Setup time, fast slew rate 2, 4 Setup time, slow slew rate 3, 4 Data before CLK↑, CLK#↓ 1.9 1 0.50 0.70 200 2.7 4.5 4 UNITS MHz ns ns V/ns ns ns Th Notes: Hold time, fast slew rate 2, 4 Hold time, slow slew rate 3, 4 Data after CLK↑, CLK#↓ 1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate of 1V/ns. 3 - For data signal input slew rate of 0.5V/ns and < 1V/ns. 4 - CLK/CLK# signal input slew rate of 1V/ns. 0.30 0.50 ns ns Switching Characteristics (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL From (Input) To (Output) VDD = 2.5V ±0.2V UNITS MIN TYP MAX fmax 200 MHz tPD CLK, CLK# Q 1.9 2.7 ns tphl RESET# Q 4.5 ns 0513F—05/13/03 5 5 Page

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