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PDF MAX1121 Data sheet ( Hoja de datos )

Número de pieza MAX1121
Descripción 250Msps Analog-to-Digital Converter
Fabricantes Maxim Integrated Products 
Logotipo Maxim Integrated Products Logotipo



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No Preview Available ! MAX1121 Hoja de datos, Descripción, Manual

19-3077; Rev 1; 2/04
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1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
General Description
The MAX1121 is a monolithic 8-bit, 250Msps analog-to-
digital converter (ADC) optimized for outstanding
dynamic performance at high IF frequencies up to
500MHz. The product operates with conversion rates of
up to 250Msps while consuming only 477mW.
At 250Msps and an input frequency of 100MHz, the
MAX1121 achieves a spurious-free dynamic range
(SFDR) of 68dBc. Its excellent signal-to-noise ratio
(SNR) of 48.9dB at 10MHz remains flat (within 0.5dB)
for input tones up to 500MHz. This makes the MAX1121
ideal for wideband applications such as digital predis-
tortion in cellular base-station transceiver systems.
The MAX1121 requires a single 1.8V supply. The ana-
log input is designed for either differential or single-
ended operation and can be AC- or DC-coupled. The
ADC also features a selectable on-chip divide-by-2
clock circuit, which allows the user to apply clock fre-
quencies as high as 500MHz. This helps to reduce the
phase noise of the input clock source. A differential
LVDS sampling clock is recommended for best perfor-
mance. The converter’s digital outputs are LVDS com-
patible, and the data format can be selected to be
either two’s complement or offset binary.
The MAX1121 is available in a 68-pin QFN with
exposed paddle (EP) and is specified over the industri-
al (-40°C to +85°C) temperature range.
For pin-compatible, higher resolution versions of the
MAX1121, refer to the MAX1122 (170Msps), the
MAX1123 (210Msps), and the MAX1124 (250Msps)
data sheets.
Applications
Wireless and Wired Broadband Communication
Digital Oscilloscopes
Digital Predistortion Receivers
Communications Test Equipment
Radar and Satellite Subsystems Antenna Array
Processing
Instrumentation
Features
250Msps Conversion Rate
SNR = 48.8dB/48.7dB at fIN = 100MHz/500MHz
SFDR = 68dBc/63.8dBc at fIN = 100MHz/500MHz
Single 1.8V Supply
477mW Power Dissipation at 250Msps
On-Chip Track-and-Hold and Internal Reference
On-Chip Selectable Divide-by-2 Clock Input
LVDS Digital Outputs with Data Clock Output
Evaluation Kit Available (Order MAX1124EVKIT)
Ordering Information
PART
TEMP RANGE
MAX1121EGK
-40°C to +85°C
*EP = Exposed paddle.
PIN-PACKAGE
68 QFN-EP*
TOP VIEW
Pin Configuration
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
AVCC 1
AGND 2
REFIO 3
REFADJ 4
AGND 5
AVCC 6
AGND 7
INP 8
INN 9
AGND 10
AVCC
AVCC
AVCC
AVCC
AGND
11
12
13
14
15
AGND 16
CLKDIV 17
EP
MAX1121
51 D4P
50 D4N
49 D3P
48 D3N
47 D2P
46 D2N
45 OGND
44 OVCC
43 DCLKP
42 DCLKN
41 OVCC
40 D1P
39 D1N
38 D0P
37 D0N
36 N.C.
35 N.C.
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX1121 pdf
www.DataSheet4U.com
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Typical Operating Characteristics
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100, TA = +25°C.)
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
0
fSAMPLE = 250.0057MHz
-10 fIN = 11.5054MHz
-20
AIN = -0.4885MHz
SNR = 48.9dB
-30 SFDR = 71.5dBc
HD2 = -79.2dBc
-40 HD3 = -74.6dBc
-50
-60 HD2 HD3
-70
-80
-90
0
20 40 60 80 100 120 140
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
0
-10
-20
FUNDAMENTAL
fSAMLE = 250.0057MHz
fIN = 500.516MHz
AIN = -0.5235MHz
SNR = 48.8dB
-30 SFDR = 63.8dBc
HD2 = -70.8dBc
-40 HD3 = -63.8dBc
-50 HD3
-60
-70 HD2
-80
-90
0
20 40 60 80 100 120 140
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
0
fSAMPLE = 250.0057MHz
-10 fIN = 60.0294MHz
-20
AIN = -0.4885MHz
SNR = 49dB
-30 SFDR = 71.1dBc
HD2 = -79.5dBc
-40 HD3 = -71.9dBc
-50
HD3 HD2
-60
-70
-80
-90
0
20 40 60 80 100 120 140
ANALOG INPUT FREQUENCY (MHz)
SNR vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
50
49
48
47
46
45
0
100 200 300 400 500
fIN (MHz)
FFT PLOT (8192-POINT DATA RECORD,
COHERENT SAMPLING)
0
fSAMPLE = 250.0057MHz
-10 fIN = 183.5064MHz
-20
AIN = -0.5245MHz
SNR = 48.8dB
-30 SFDR = 69.1dBc
HD2 = -77.2dBc
-40 HD3 = -69.1dBc
-50
-60 HD3
-70
HD2
-80
-90
0
20 40 60 80 100 120 140
ANALOG INPUT FREQUENCY (MHz)
SFDR vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
80
74
68
62
56
50
0
100 200 300 400 500
fIN (MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 250.0057MHz, AIN = -0.5dBFS)
-50
-60 HD3
-70
-80
HD2
-90
-100
0
100 200 300 400 500
fIN (MHz)
SNR vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 250.0057MHz, fIN = 60.0294MHz)
50
45
40
35
30
25
20
-30
-25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
SFDR vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 250.0057MHz, fIN = 60.0294MHz)
75
70
65
60
55
50
45
40
35
30
-30
-25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
_______________________________________________________________________________________ 5

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MAX1121 arduino
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1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
SAMPLING EVENT
INN
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INP
CLKN
CLKP
DCLKP
DCLKN
tAD
N
tCPDL
N-8
tPDL
N+1
tLATENCY
N-7
tCH
N+8
tCL
N+9
N
tCPDL - tPDL
N+1
D0P/N–D7P/N
ORP/N
N-8
N-7 N-1
N
tCPDL - tPDL ~ 0.4 x tSAMPLE with tSAMPLE = 1 / fSAMPLE
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
Figure 4. System and Output Timing Diagram
N+1
and are usually driven in AC-coupled configuration.
See the Differential, AC-Coupled Clock Input in the
Applications Information section for more circuit details
on how to drive CLKP and CLKN appropriately.
Although not recommended, the clock inputs also
accept a single-ended input signal.
The MAX1121 also features an internal clock manage-
ment circuit (duty-cycle equalizer) that ensures that the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty cycle clock signal,
which desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum clock fre-
quency of >20MHz to work appropriately and accord-
ing to data sheet specifications.
Clock Outputs (DCLKP, DCLKN)
The MAX1121 features a differential clock output, which
can be used to latch the digital output data with an
external latch or receiver. Additionally, the clock output
can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
2.1ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See Figure 4 for timing details.
VOP
2.2k
VON
2.2k
Figure 5. Simplified LVDS Output Architecture
OVCC
OGND
______________________________________________________________________________________ 11

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