DataSheet.es    


PDF MAX1429 Data sheet ( Hoja de datos )

Número de pieza MAX1429
Descripción 15-Bit 100Msps ADC
Fabricantes Maxim Integrated Products 
Logotipo Maxim Integrated Products Logotipo



Hay una vista previa y un enlace de descarga de MAX1429 (archivo pdf) en la parte inferior de esta página.


Total 18 Páginas

No Preview Available ! MAX1429 Hoja de datos, Descripción, Manual

19-3434; Rev 0; 10/04
15-Bit, 100Msps ADC with -77.7dBFSEVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
Noise Floor for Baseband Applications
General Description
The MAX1429 is a 5V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a fully differ-
ential wideband track-and-hold (T/H) and a 15-bit con-
verter core. The MAX1429 is optimized for multichannel,
multimode receivers, which require the ADC to meet very
stringent dynamic performance requirements. With a
noise floor of -77.7dBFS, the MAX1429 allows for the
design of receivers with superior sensitivity.
The MAX1429 achieves two-tone, spurious-free dynamic
range (SFDR) of -100dBc for input tones of 10MHz and
15MHz. Its excellent signal-to-noise ratio (SNR) of 75.1dB
and single-tone SFDR performance (SFDR1/SFDR2) of
90dBc/94dBc at fIN = 15MHz and a sampling rate of
80Msps make this part ideal for high-performance digital
receivers.
The MAX1429 operates from an analog 5V and a digital
3V supply, features a 2.2VP-P full-scale input range,
and allows for a sampling speed of up to 100Msps. The
input T/H operates with a -1dB full-power bandwidth of
260MHz.
The MAX1429 features parallel, CMOS-compatible out-
puts in two’s-complement format. To enable the interface
with a wide range of logic devices, this ADC provides a
separate output driver power-supply range of 2.3V to
3.5V. The MAX1429 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Note that IF parts MAX1418, MAX1428, and MAX1430
(see Pin-Compatible Higher/Lower Speed Versions
Selection table) are recommended for applications that
require high dynamic performance for input frequen-
cies greater than fCLK/3. The MAX1429 is optimized for
input frequencies of less than fCLK/3.
Features
100Msps Minimum Sampling Rate
-77.7dBFS Noise Floor
Excellent Dynamic Performance
75.1dB SNR at fIN = 15MHz and AIN = -1dBFS
90dBc/94dBc Single-Tone SFDR1/SFDR2 at
fIN = 15MHz and AIN = -1dBFS
-100dBc Multitone SFDR at fIN1 = 10MHz
and fIN2 = 15MHz
Less than 0.25ps Sampling Jitter
Fully Differential Analog Input Voltage Range of
2.2VP-P
CMOS-Compatible Two’s-Complement Data Output
Separate Data Valid Clock and Overrange Outputs
Flexible-Input Clock Buffer
EV Kit Available for MAX1429
(Order MAX1427EVKIT)
Ordering Information
PART
MAX1429ETN
TEMP RANGE
-40°C to +85°C
*EP = Exposed paddle.
PIN-PACKAGE
56 Thin QFN-EP*
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Single- and Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
Power Amplifier Linearity Correction
Antenna Array Processing
Pin-Compatible Higher/Lower
Speed Versions Selection
PART
MAX1418
MAX1419
MAX1427
MAX1428
MAX1429
MAX1430
SPEED GRADE
(Msps)
65
65
80
80
100
100
TARGET
APPLICATION
IF
Baseband
Baseband
IF
Baseband
IF
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX1429 pdf
www.DataSheet4U.com
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
Typical Operating Characteristics
(AVCC = 5V, DVCC = DRVCC = 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially
with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 100MHz, TA = +25°C. All AC data is based on a 32k-point
FFT record and under coherent sampling conditions.)
FFT PLOT (32,768-POINT DATA RECORD,
FFT PLOT (32,768-POINT DATA RECORD,
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
COHERENT SAMPLING)
COHERENT SAMPLING)
000
fCLK = 100.0997MHz
fCLK = 100.0997MHz
fCLK = 100.0997MHz
-20
fIN = 10.0014MHz
AIN = -1.05dBFS
-20
fIN = 15.0021MHz
AIN = -0.96dBFS
-20
fIN = 34.9973MHz
AIN = -1.01dBFS
SNR = 75.6dBc
SNR = 75.3dBc
SNR = 75dBc
-40
SINAD = 75.4dBc
-40
SINAD = 74.8dBc
-40 SINAD = 70.6dBc
SFDR1 = 90dBc
SFDR1 = 86.7dBc
SFDR1 = 73dBc
-60
SFDR2 = 96.4dBc
HD2 = -91dBFS
-60
SFDR2 = 93.9dBc
HD2 = -87.6dBFS
SFDR2 = 93.9dBc
-60 HD2 = -83.6dBFS
HD3 = -95.5dBFS
HD3 = -90.2dBFS
HD3 = -74dBFS
-80 -80 -80
-100 -100 -100
-120
0
5 10 15 20 25 30 35 40 45 50
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT (32,768-POINT DATA
RECORD, COHERENT SAMPLING)
0
-20
-40 fIN1
fCLK = 100.0997MHz
fIN1 = 10.1022MHz
AIN1 = -7.09dBFS
fIN2 = 15.0021MHz
fIN2 AIN2 = -7dBFS
IMD = -84.9dBc
-60
fIN2 - fIN1
-80
fIN1 + fIN2
-100
-120
0
5 10 15 20 25 30 35 40 45 50
ANALOG INPUT FREQUENCY (MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fCLK = 100.0997MHz, AIN = -1dBFS)
-65
-70
-75 HD3
-80
-85
-90
HD2
-95
-100
-105
5
10 15 20 25 30 35 40 45 50
fIN (MHz)
-120
0
5 10 15 20 25 30 35 40 45 50
ANALOG INPUT FREQUENCY (MHz)
SNR vs. ANALOG INPUT FREQUENCY
(fCLK = 100.0997MHz, AIN = -1dBFS)
77
76
75
74
73
72
71
70
5
10 15 20 25 30 35 40 45 50
fIN (MHz)
SNR vs. SAMPLING FREQUENCY
(fIN = 15MHz, AIN = -1dBFS)
78
77
76
75
74
73
72
71
70
20 30 40 50 60 70 80 90 100
fCLK (MHz)
-120
0
5 10 15 20 25 30 35 40 45 50
ANALOG INPUT FREQUENCY (MHz)
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(fCLK = 100.0997MHz, AIN = -1dBFS)
115
105 SFDR2
95
85
75
SFDR1
65
55
5
10 15 20 25 30 35 40 45 50
fIN (MHz)
SFDR1/SFDR2 vs. SAMPLING FREQUENCY
(fIN = 15MHz, AIN = -1dBFS)
105
100 SFDR2
95
90
85
80
SFDR1
75
70
20 30 40 50 60 70 80 90 100
fCLK (MHz)
_______________________________________________________________________________________ 5

5 Page





MAX1429 arduino
www.DataSheet4U.com
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applications
tDGV: Time from the rising edge of the clock until data
is guaranteed to be valid
tSETUP: Time from data guaranteed valid until the ris-
ing edge of DAV
tHOLD: Time from the rising edge of DAV until data is
no longer valid
tCLKP: Time from the 50% point of the rising edge to
the 50% point of the falling edge of the clock signal
tCLKN: Time from 50% point of the falling edge to the
50% point of the rising edge of the clock signal
The MAX1429 samples the input signal on the rising
edge of the input clock. Output data is valid on the ris-
ing edge of the DAV signal, with a data latency of three
clock cycles. Note that the clock duty cycle must be
50% ±5% for proper operation.
Digital Outputs (D0–D14, DAV, DOR)
The logic “high” level of the CMOS-compatible digital
outputs (D0–D14, DAV, and DOR) may be set in the
2.3V to 3.5V range. This is accomplished by setting the
voltage at the DVCC and DRVCC pins to the desired
logic-high level. Note that the DVCC and DRVCC volt-
ages must be the same value.
For best performance, the capacitive loading on the digital
outputs of the MAX1429 should be kept as low as possible
(<10pF). Large capacitive loads result in large charging
currents during data transitions, which may feed back into
the analog section of the ADC and create distortion terms.
The loading capacitance is kept low by keeping the output
traces short and by driving a single CMOS buffer or latch
input (as opposed to multiple CMOS inputs).
Inserting small series resistors (220or less) between
the MAX1429 outputs and the digital load, placed as
closely as possible to the output pins, is helpful in con-
trolling the size of the charging currents during data
transitions and can improve dynamic performance.
Keep the trace length from the resistor to the load as
short as possible to minimize trace capacitance.
The output data is in two’s complement format, as illus-
trated in Table 1.
Data is valid at the rising edge of DAV (Figure 4), and
DAV may be used as a clock signal to latch the output
data. The DAV output provides twice the drive strength
of the data outputs, and may therefore be used to drive
multiple data latches.
The DOR output is used to identify an overrange condi-
tion. If the input signal exceeds the positive or negative
full-scale range for the MAX1429, then DOR is asserted
high. The timing for DOR is identical to the timing for
the data outputs, and DOR therefore provides an over-
range indication on a sample-by-sample basis.
Table 1. MAX1429 Digital Output Coding
INP
ANALOG VOLTAGE LEVEL
INN
ANALOG VOLTAGE LEVEL
VREF + 0.64V
VREF - 0.64V
VREF
VREF
VREF - 0.64V
VREF + 0.64V
D14–D0
TWO’S COMPLEMENT CODE
011111111111111
(positive full scale)
000000000000000
(midscale + δ)
111111111111111
(midscale - δ)
100000000000000
(negative full scale)
______________________________________________________________________________________ 11

11 Page







PáginasTotal 18 Páginas
PDF Descargar[ Datasheet MAX1429.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
MAX142012-Bit / 60Msps / +3.3V / Low-Power ADC with Internal ReferenceMaxim Integrated
Maxim Integrated
MAX1420CCM12-Bit / 60Msps / +3.3V / Low-Power ADC with Internal ReferenceMaxim Integrated
Maxim Integrated
MAX1420ECM12-Bit / 60Msps / +3.3V / Low-Power ADC with Internal ReferenceMaxim Integrated
Maxim Integrated
MAX142112-Bit / 40Msps / +3.3V / Low-Power ADC with Internal ReferenceMaxim Integrated
Maxim Integrated

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar